Enhanced salicidation technique

Abstract

A semiconductor fabrication process in which enhanced salicidation and reliability is achieved by implanting a silicon bearing species and a nitrogen bearing species into the source/drain regions and polysilicon regions of an integrated circuit transistor prior to the silicide formation sequence. A gate dielectric is formed on an upper surface of a semiconductor substrate. The substrate includes an active region that is laterally disposed between a pair of isolation structures. The active region includes a channel region that is laterally disposed between a pair of source/drain regions. A conductive gate structure is formed on the upper surface of the semiconductor substrate aligned over the channel region A silicon bearing species is then implanted or otherwise introduced into the conductive gate structure and into the source/drain regions to form amorphous silicon rich regions proximal to respective upper surfaces of the source/drain regions and the conductive gate structure. A nitrogen bearing species is then implanted into the conductive gate source/drain regions and a source/drain impurity distribution is introduced into the source/drain regions. A self aligned silicide process, in which a refractory metal is deposited upon the substrate upper surface and heated to a reaction temperature to form a silicide compound over exposed silicon regions of the substrate, preferably follows the formation of the source/drain regions

Dependencies are inferred from the claim text.