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US 6,306,744 B1Granted
Filter capacitor construction
AssigneeUnited Microelectronics Corp.
InventorLarry L. Aldrich
Life of this patent
Estimating the term…
Abstract
An integrated circuit having a voltage source and a plurality of conductive power bus tiers extending across the integrated circuit. Each of the power bus tiers are electrically coupled in parallel to the voltage source. The integrated circuit includes a filter capacitor having a first plate and a second plate that are separated by a capacitor dielectric. The first plate forms a bus strap coupling to each of the plurality of power bus tiers.
Claims6
A method for making an integrated circuit comprising the steps of:
- providing a first voltage source;
- providing a substrate;
- forming integrated circuitry in selected first portions of the substrate;
- forming a plurality of first conductive power bus tiers on the substrate wherein each of the first conductive power bus tiers are electrically coupled in parallel to the first voltage source;
- forming a plurality of filter capacitors in selected second portions of the substrate, wherein the filter capacitors comprise a first plate and a second plate which are separated by a capacitor dielectric and the first plate forms a bus strap coupling to each of the plurality of first conductive power bus tiers;
- forming a third plate formed in a common plane with the first plate and separated from the second plate by a capacitor dielectric;
- providing a second voltage source;
- forming a plurality of second conductive power bus tiers on the substrate wherein each of the second conductive power bus tiers are electrically coupled in parallel to the second voltage source and the third plate forms a bus strap coupling to each of the plurality of second conductive power bus tiers.
5 more elements
A method of laying out an integrated circuit (IC) to generate an IC layout, the method comprising the steps of:
- laying out integrated circuitry in active device areas of the IC layout, wherein the active device areas when excluded from the total IC area define open areas on the IC layout;
- providing a first voltage source;
- laying out a plurality of first conductive power supply bus tiers in the open areas of the IC layout wherein each of the first conductive power bus tiers are electrically coupled in parallel to the first voltage source;
- laying out a plurality of filter capacitors in the open areas of the substrate, wherein each of the plurality of filter capacitors comprise a first plate and a second plate which are separated by a capacitor dielectric, such that the first plate and each of the plurality of first conductive power bus tiers overlap at multiple locations;
- laying out vias in the multiple locations;
- laying out a third plate formed in a common plane with the first plate and separated from the second plate by a capacitor dielectric;
- providing a second voltage source;
- laying out a plurality of second conductive power supply bus tiers in the open areas of the IC layout wherein each of the second conductive power bus tiers are electrically coupled in parallel to the second voltage source, and the third plate and each of the plurality of second conductive power bus tiers overlap at multiple locations;
- and
- laying out vias in the multiple overlap locations.
7 more elements
Dependencies are inferred from the claim text.