Method to reduce source-line resistance in flash memory with sti
AssigneeTexas Instruments Incorporated
InventorsFreidoon Mehrad, Thomas M. Ambrose, Lancy Y. Tsung
Life of this patent
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Abstract
A method of forming a semiconductor component having a conductive line (24) that crosses a trench (72). The method involves forming steps (104) in the sidewalls of the trench (72) in a semiconductor substrate (52). A dopant may be implanted at a first energy level into the semiconductor substrate (52) to form a first conductive region (92). The dopant may be implanted at a second energy level into the semiconductor substrate (52) to form a second conductive region (94). The first energy level may be greater than the second energy level. The first conductive region (92) and the second conductive region (94) may form the conductive line (24).
Claims14
A method of forming an electronic device having a conducting line, said method comprising:
- a) forming trenches in a semiconductor layer, said trenches having a top, a bottom, and sidewalls;
- b) forming a plurality of steps in said sidewalls of said trenches;
- and
- c) providing a dopant into said steps of said sidewalls of said trenches.
A method of forming a semiconductor device component having a conductive line that crosses a trench filled with a dielectric material, said trench having a plurality of sidewall surfaces and a base surface, the method comprising the steps of:
- a) etching said dielectric material to a first level exposing a portion of said sidewall surfaces whereby said first level is above said trench base surface;
- b) oxidizing said exposed portion of said sidewall surfaces;
- c) etching said dielectric material to a second level exposing said sidewall surfaces whereby said second level is below said first level;
- d) repeating steps a), b), and c) until said base surface is exposed;
- and
- e) implanting a dopant into the said trench to form a conductive line.
Dependencies are inferred from the claim text.