US 6,306,721 B1Granted

Method of forming salicided poly to metal capacitor

AssigneeChartered Semiconductor Maufacturing Ltd.

InventorsYeow Meng Teo, Madhusudan Mukhopadhyay, Heng Jee Kiat

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Abstract

A new method is provided for the creation of a salicided polysilicon capacitor. A salicided layer of polysilicon is created as the lower plate of a salicided polysilicon capacitor over the surface of a field isolation region. A layer of silicon nitride is deposited over the field oxide isolation region including the surface of the salicided polysilicon layer. A layer of TEOS is deposited over the surface of the layer of silicon nitride, a layer if titanium nitride is deposited over the surface of the layer of TEOS. The layer of TiN is etched after which the layer of TEOS is etched. The etch of the layer of TEOS is an overetch whereby TEOS is symmetrically removed from underneath the etched layer of TiN, leaving remnants of TEOS in place underneath the etched layer of TiN while at the same time creating air gaps underneath the etched layer of TiN. A layer of silane based oxide is deposited over the surface of the field oxide isolation region including the surface of the etched layer of TiN, thus enclosing the air gaps that have been created underneath the etched layer of TiN. The latter layer of silane based oxide is patterned and etched, forming the upper plate of the salicided polysilicon capacitor. The TEOS remnants remaining in place underneath the etched layer of TiN is part of the dielectric layer of the capacitor.

Claims24

Dependent claims

A method of forming a salicided polysilicon to metal capacitor as part of a semiconductor device, comprising the steps of:

providing a semiconductor substrate as a base for the salicided polysilicon to metal capacitor, an isolation region of field oxide having been provided on the surface of the substrate;
forming a layer of polysilicon on the surface of the region of field oxide, patterning and etching said layer of polysilicon, forming a patterned layer of polysilicon overlying said layer of field oxide;
saliciding the surface of the patterned and etched layer of polysilicon, forming a first conductor element;
depositing a layer of etch stop material over the surface of the region of field oxide, including the surface of the salicided layer of polysilicon;
depositing a layer of dielectric over the surface of the layer of etch stop material;
depositing a layer of. refractory metal over the surface of the layer of dielectric;
etching said layer of refractory metal, creating a pattern of refractory metal, said pattern of refractory metal aligning with said patterned and etched layer of polysilicon;
etching said layer of dielectric down to the layer of etch stop material using said patterned layer of refractory metal as a mask, partially exposing the surface of said etch stop layer, partially removing said layer of dielectric from underneath said pattern of refractory metal;
cleaning the surface of the pattern of refractory metal and the surface of said partially exposed etch stop layer;
depositing a layer of silane based oxide over the surface of said pattern of refractory metal and the surface of said partially exposed etch stop layer, enclosing areas underneath said pattern of refractory metal from which said layer of dielectric has been partially removed;
and
etching said layer of silane based oxide, partially exposing the surface of said pattern of refractory metal creating a second conductor element, partially exposing the surface of said layer of etch stop material, thereby further enclosing areas underneath said pattern of refractory metal from which said layer of dielectric has been partially removed.

9 more elements

A method of forming a salicided polysilicon to metal capacitor as part of a semiconductor device, comprising the steps of:

providing a semiconductor substrate as the base for the salicided polysilicon to metal capacitor, an isolation region of field oxide having been provided on the surface of the substrate;
forming a layer of polysilicon on the surface of the region of field oxide, patterning and etching said layer of polysilicon, forming a patterned layer of polysilicon overlying said layer of field oxide having been provided on the surface of the substrate;
saliciding the surface of the patterned and etched layer of polysilicon, forming a first conductor element;
depositing a layer of silicon nitride over the surface of the region of field oxide, including the surface of the salicided layer of polysilicon;
depositing a layer of tetra-ethyl-ortho-silicate (TEOS) over the surface of the layer of etch stop material;
depositing a layer of titanium nitride over the surface of the layer of dielectric;
etching said layer of titanium nitride, creating a pattern of titanium nitride, said pattern of titanium nitride aligning with said patterned and etched layer of polysilicon;
etching said layer of tetra-ethyl-ortho-silicate down to the layer of silicon nitride using said pattern of titanium nitride as a mask, partially exposing the surface of said layer of silicon nitride, partially removing said layer of tetra-ethyl-ortho-silicate from underneath said pattern of titanium nitride;
cleaning the surface of the pattern of titanium nitride and the surface of said partially exposed layer of silicon nitride;
depositing a layer of silane based oxide over the surface of said pattern of titanium nitride and the surface of said partially exposed layer of silicon nitride, enclosing areas underneath said pattern of titanium nitride from which said layer of tetra-ethyl-ortho-silicate has been partially removed;
and
etching said layer of silane based oxide, partially exposing the surface of said pattern of titanium nitride creating a second conductor element, further partially exposing the surface of said layer of silicon nitride, thereby further completing enclosing areas underneath said pattern of titanium nitride from which said layer of tetra-ethyl-ortho-silicate has been partially removed.

9 more elements

Dependencies are inferred from the claim text.