Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer

A method of manufacturing a semiconductor device on a semiconductor substrate, comprising the steps of:

• forming a plurality of multi-layer structures on the semiconductor substrate to form core and peripheral regions;
• forming sidewall spacers by anisotropic etching around the plurality of the multi-layer structures;
• forming source and drain regions by ion implantation in the semiconductor substrate adjacent the sidewall spacers;
• depositing a etch stop layer over the semiconductor substrate, including the plurality of multi-layer structures, the sidewall spacers, the source and drain regions;
• depositing a dielectric layer over the etch stop layer,
• depositing a photoresist contact mask over the dielectric layer;
• photolithographically processing the photoresist contact mask to expose portions of the dielectric layer over the core region and to cover the dielectric layer over the peripheral region;
• anisotropically etching portions of the dielectric layer and portions of the etch stop layer over the semiconductor substrate between the plurality of multi-layer structures using the photoresist contact mask in the core region to form core contact openings;
• forming secondary sidewall spacers by anisotropic etching in the core contact openings over exposed portions of the plurality of multi-layer structures;
• depositing a second photoresist contact mask over the dielectric layer and in the secondary sidewall spacers;
• photolithographically processing the second photoresist contact mask to cover the core region and to expose portions of the dielectric layer over the peripheral region;
• anisotropically etching portions of the dielectric layer and the etch stop layer over the source and drain regions and portions of the plurality of multi-layer structures in the peripheral region using the second photoresist contact mask to form peripheral local interconnect openings;
• depositing a conductive material over the dielectric layer and in the core and peripheral contact openings;
• and
• chemical mechanical polishing the conductive material over the dielectric layer whereby the conductive material is left isolated in the core contact and peripheral local interconnect openings.