Nonvolatile ferroelectric memory
AssigneeHyundai Electronics Industries Co., Ltd.
InventorsHee Bok Kang, Doo Young Yang
Life of this patent
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Abstract
A nonvolatile ferroelectric memory comprising a main memory cell blocks including first and second wordlines, a first cell transistor whose gate is connected to the first wordline and one electrode which is connected to a bitline, a second transistor whose gate is connected to the second wordline and one electrode which is connected to a bit bar line, a first ferroelectric capacitor whose first electrode is connected to the other electrode of the first transistor. Also including reference cell blocks formed to correspond to the main memory cell blocks for reading out data of the memory cell blocks.
Claims23
A method for forming a nonvolatile ferroelectric memory comprising:
- forming a gate layer on a surface of a semiconductor substrate including an active region and selectively patterning the gate layer to form first and second wordlines;
- implanting impurity ions into the active region using the first and second wordlines as masks to form source/drain regions;
- forming an interlevel insulating layer on the surface of the semiconductor substrate and selectively patterning the interlevel insulating layer to expose any one region of the source/drain regions, thereby forming a storage node contact hole;
- forming a capacitor first electrode material layer on the surface of the interlevel insulating layer including the storage node contact hole and selectively patterning the capacitor first electrode material layer to form a capacitor first electrode;
- forming a ferroelectric layer on the capacitor first electrode and selectively implanting impurity ions into a portion of the ferroelectric layer to form a resistor region;
- and
- forming a bitline contacted with the other region of the source/drain regions.
A method for forming a ferroelectric device comprising:
- forming a patterned gate material layer on a semiconductor substrate including an active region, the patterned gate material layer forming first and second wordlines;
- forming source and drain regions electrically coupled to the first and second wordlines;
- forming a patterned interlevel insulating layer over the wordlines and the semiconductor substrate, the interlevel insulating layer having a portion configured to expose any one region of the source/drain regions, thereby forming a contact hole;
- forming a capacitor first electrode material layer on the interlevel insulation layer and in the storage node contact hole to form a capacitor first electrode;
- forming a ferroelectric layer on a first portion of the capacitor first electrode;
- forming a resistor in a portion of the ferroelectric layer;
- forming a capacitor second electrode on a portion of the ferroelectric layer and a portion of the resistor;
- forming a bitline contacted with the other region of the source/drain regions.
A method for forming a ferroelectric device comprising:
- forming a patterned gate material layer on a semiconductor substrate including an active region, the patterned gate material layer forming first and second wordlines;
- forming source and drain regions electrically coupled to the first and second wordlines;
- forming a patterned interlevel insulating layer on the surface of the semiconductor substrate having a portion configured to expose any one region of the source/drain regions, thereby forming a storage node contact hole;
- forming a capacitor first electrode material layer on the interlevel insulation layer and in the storage node contact hole to form a capacitor first electrode;
- forming a ferroelectric layer on a first portion of the capacitor first electrode;
- forming a resistor layer on a second portion of the capacitor first electrode;
- forming a capacitor second electrode on a portion of the ferroelectric layer and a portion of the resistor layer;
- forming a bitline contacted with the other region of the source/drain regions.
A method for forming a ferroelectric device comprising:
- forming a capacitor lower electrode on a substrate;
- forming a ferroelectric layer on the capacitor lower electrode;
- converting a portion of the ferroelectric layer into a resistor;
- and
- forming a capacitor upper electrode on the ferroelectric layer.
Dependencies are inferred from the claim text.