Memory array having a digit line buried in an isolation region and method for forming same

A method for forming a memory array having first and second memory cells, the method comprising:

• forming an isolation trench in a semiconductor substrate;
• forming a conductive line in the trench;
• forming a first insulator on the substrate;
• forming at least one isolation segment through the first insulator and into the substrate to define at least one active area of the substrate;
• forming first and second gates of the memory cells on the insulator in the at least one active area;
• forming in the substrate a first source/drain region adjacent to the first gate, a second source/drain region adjacent to the second gate, and a shared source/drain region between the first and second gates;
• and
• electrically coupling the shared source/drain region to the conductive line.

A method for forming a memory array having a pair of adjacent memory cells, the method comprising:

• forming an isolation trench in a semiconductor substrate;
• forming a conductive line in the trench;
• forming first and second isolation segments in the substrate, the isolation segments adjacent to and substantially perpendicular to the isolation trench;
• forming a first insulator on the substrate between the isolation segments;
• forming first and second gates of the memory cells on the insulator;
• forming in the substrate a first source/drain region between the first gate and the first isolation segment, a second source/drain region between the second gate and the second isolation region, and a shared source/drain region between the first and second gates;
• electrically coupling the shared source/drain region to the line;
• forming a mandrel layer on exposed regions of the substrate, isolation trench, isolation segments, and gates;
• forming a first trench in the mandrel layer, the first trench having a first sidewall that is over the first gate and a second sidewall that is over the first isolation segment;
• filling the trench with a conductive material;
• and
• anisotropically etching the conductive material to form first and second word lines along the first and second sidewalls, respectively, the first word line being electrically coupled to the first gate.

A method for forming a memory array having a plurality of memory cells, the method comprising:

• forming a gate insulator on a substrate;
• forming a gate conductor on the gate insulator;
• forming a pad insulator on the gate conductor, the pad insulator having a surface;
• forming first isolation trenches that extend through the pad insulator, gate conductor, and gate insulator, and into the substrate;
• lining the trenches with a trench insulator;
• filling the lines trenches with a first conductive material to form a bit line;
• covering the filled trenches with a cap insulator;
• forming isolation segments between adjacent ones of the first trenches to define active regions of the substrate;
• forming from the gate conductor a pair of gate segments in each active region, the pair of gate segments separated from each other by a common region of the substrate and from adjacent ones of the isolation segments by first and second uncommon regions of the substrate, respectively;
• removing the gate insulator from the common regions;
• exposing respective portions of the bit line that are adjacent to the common regions;
• forming insulator side walls on the gate segments;
• and
• forming a conductive strap between each of the common regions and a respective exposed portion of the bit line.

A method for forming a memory array having a plurality of memory cells, the method comprising:

• forming a pad structure on a substrate, the pad structure having a surface;
• forming first isolation trenches that extend through the pad structure and into the substrate;
• lining the trenches with a trench dielectric;
• filling the lined trenches with a first conductive material to form a bit line;
• covering the filled trenches with a cap dielectric;
• forming isolation segments between adjacent ones of the first trenches to define active areas of the substrate;
• forming a gate dielectric on the active areas of the substrate;
• forming a gate conductor on the gate dielectric;
• forming from the gate conductor a pair of gate segments in each active area, the pair of gate segments separated from each other by a shared area of the substrate and from adjacent ones of the isolation segments by first and second unshared areas of the substrate, respectively;
• removing the gate dielectric from the shared areas;
• exposing portions of the bit line that are adjacent to the shared areas;
• forming dielectric side walls on the gate segments;
• and
• forming a conductive line between each of the shared areas and a respective exposed portion of the bit line.

A method for forming a memory array having a memory cell, the method comprising:

• forming an isolation trench in a semiconductor substrate;
• forming a conductive path within the trench;
• forming a first insulator on the substrate;
• forming a conductive gate layer on the first insulator;
• forming an insulative pad layer on the conductive gate layer;
• forming a gate of the memory cell, wherein forming the gate includes etching the insulative pad layer and the conductive gate layer;
• forming first and second source/drain regions of the memory cell in the substrate proximate the gate;
• and
• conductively coupling the first source/drain region to the conductive path.