US 6,306,702 B1Granted

Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length

AssigneeAdvanced Micro Devices, Inc.

InventorsMing Yin Hao, Richard P. Rouse, Zicheng Gary Ling

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Abstract

CMOS transistors, i.e., N- and P-type transistors, are formed with substantially the same gate length and source/drain regions with lightly doped extensions. Embodiments include sequentially: ion implanting an N-type impurity, e.g. As, to form the N- type transistor shallow source/drain implants; forming relatively thin first sidewall spacers on the gates of both transistors; ion implanting a P-type impurity, e.g. BF2, to form shallow source/drain extension implants for the P-type transistor; forming relatively thick side wall spacers on the first sidewall spacers of both transistors; ion implanting, e.g. As, to form moderately or heavily doped N-type implants; activation annealing at a first temperature, e.g., about 1050° C. to form the shallow N- and P-type source/drain extensions and moderately or heavily doped P-type source/drain regions; ion implanting a P-type impurity, e.g., BF2, to form moderately or heavily doped P-type source/drain implants; and activation annealing at a second temperature less than the first temperature, e.g., at about 1000° C. to form moderately or heavily doped P type source/drain regions.

Claims14

Dependent claims

A method of manufacturing a semiconductor device containing NMOS and PMOS transistors having substantially the same gate lengths, the method comprising, in order, the steps of:

(a) forming polysilicon gates having side surfaces for both the NMOS and PMOS transistors on a substrate;
(b) masking the gate for the PMOS transistor and ion implanting an N-type impurity to form lightly doped source/drain extension implants for the NMOS transistor;
(c) removing the mask and forming first insulating sidewall spacers, having a first thickness, on the side surfaces of each of the gates for the NMOS and PMOS transistors;
(d) masking the gate for the NMOS transistor and ion implanting a P-type impurity to form lightly doped source/drain extension implants for the PMOS transistor;
(e) removing the mask and forming second insulating sidewall spacers on the first insulating sidewall spacers, the second insulating sidewall spacers having a second thickness, greater than the first thickness;
(f) masking the gate for the PMOS transistor and ion implanting an N-type impurity to form moderately or heavily doped source/drain implants for the NMOS transistor;
(g) removing the mask and activation annealing at a first temperature to form moderately or heavily doped source/drain regions of the NMOS transistor;
(h) masking the gate for the NMOS transistor and ion implanting a P-type impurity to form moderately or heavily doped source/drain implants of the PMOS transistor;
and
(i) removing the mask and activation annealing at a second temperature, lower than the first temperature, to form moderately or heavily doped source/drain regions of the PMOS transistor.

7 more elements

A method of manufacturing a semiconductor device containing NMOS and PMOS transistors having substantially the same gate lengths, the method comprising, in order, the steps of:

(a) forming a first gate for the NMOS transistor, the first gate having side surfaces on a first portion of a substrate which is either a P-doped substrate or a P-well in a N-doped substrate;
(b) forming a second gate for the PMOS transistor, the second gate having side surfaces on a second portion of the substrate which is either an N-doped substrate or an N-well in a P-doped substrate;
(c) masking the gate for the PMOS transistor and ion implanting an N-type impurity to form shallow lightly doped source/drain extension implants for the NMOS transistor, the N-type impurity ion implanting being conducted at a dosage of about 2.0×10+14 to about 2.0×10+15 atoms cm−2 at an energy about 3 to about 10 KeV;
(d) removing the mask and forming first insulating sidewall spacers, having a first thickness of about 100 Å to about 500 Å, on the side surfaces of each of the gates for the NMOS and PMOS transistors;
(e) masking the gate for the NMOS transistor and ion implanting a P-type impurity to form shallow lightly doped source/drain extension implants for the PMOS transistor, the P-type ion implanting being conducted and a dosage of about 1.0×10+14 to about 2.0×10+15 atoms cm−2 at an energy about 3 to about 10 KeV;
(f) removing the mask and forming second insulating sidewall spacers on the first insulating sidewall spacers, the second insulating sidewall spacers having a second thickness, greater than the first thickness, and in the range of about 300 Å to about 1000 Å
(g) masking the gate for the PMOS transistor and ion implanting an N-type impurity at a dosage of about 1.0×10+15 about 4×10+15 atoms cm−2 and an energy about 20 to about 40 KeV, to form moderately or heavily doped source/drain implants for the NMOS transistor;
(h) removing the mask and activation annealing at a first temperature of about 1000° C. to about 1050° C. to form moderately or heavily doped source/drain regions of the NMOS transistor;
(i) masking the gate for the NMOS transistor and ion implanting a P-type impurity at a dosage of about 1.0×10+15 to about 4.0×10+15 atoms cm−2 and an energy about 15 to about 30 KeV, to form moderately or heavily doped source/drain implants for the PMOS transistor;
and
(j) removing the mask and activation annealing at a second temperature of about 950° C. to about 1025° C. to form moderately or heavily doped source/drain regions of the PMOS transistor.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/379,627Filed 24 Aug 1999
Granted: 23 Oct 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/0184
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate sidewall spacers
H10D
Inorganic electric semiconductor devices