Self-aligned contact process
AssigneeUnited Microelectronics Corp.
InventorWen-Kuan Yeh
Life of this patent
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AssigneeUnited Microelectronics Corp.
InventorWen-Kuan Yeh
Estimating the term…
A self-aligned contact process. A substrate is provided. A gate including a polysilicon layer and a metal silicide layer is formed on the substrate. A cap layer is formed on the gate to protect the gate. A first spacer is formed on the sidewall of the gate. A first ion implantation is performed using the gate and the first spacer as a first mask to form lightly doped regions in the substrate. A conformal liner layer is formed on the cap layer, the first spacer and the substrate. An insulating layer is formed on the conformal liner layer. A part of the insulating layer and a part of the liner layer are removed until exposing the cap layer. A part of the liner layer remaining on the first spacer and a part of the insulating layer remaining on the remaining liner layer are used as a second spacer. A second ion implantation is performed to form source/drain regions with lightly doped drain (LDD) structures in the substrate beside the second spacer. An inter-layer dielectric layer is formed over the substrate and then is etched to form a contact opening therein that exposes a part of the source/drain regions.
A self-aligned contact process for formation of a contact opening on a semiconductor substrate comprising:
A self-aligned contact process for formation of a contact opening on a semiconductor substrate, comprising:
Dependencies are inferred from the claim text.