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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJian-Hsing Lee, Jiaw-Ren Shih, Shui-Hung Chen, Yi-Hsun Wu
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An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors. When contacting an ESD voltage source to the collectors of the plurality of parasitic bipolar junction transistors, the junction formed between the collector and the base of the parasitic bipolar junction transistor enters into avalanche breakdown. The avalanche breakdown generates a large current through the substrate bulk resistances that is sufficiently large as to cause the base emitter junctions of all the parasitic bipolar junction transistors and turn on the parasitic bipolar junction transistors. The conduction of all the parasitic bipolar junction transistors is sufficient to cause the ESD voltage to be discharged thus preventing damage to the internal circuitry.
A method to form an ESD circuit within a substrate comprising the steps of:
Dependencies are inferred from the claim text.