Skew calibration means and a method of skew calibration

A memory test system for testing synchronous semiconductor devices comprising:

• a timing means;
• a fault logic means;
• a central control unit;
• and
• a tester header including
• a plurality of drivers comprising at least one input register connectable to an input pin of a device under test for transmitting signals;
• a plurality of receivers comprising at least one output register connectable to an output pin of the device under test for receiving signals;
• and
• a reference clock;
• wherein said reference clock is operable to calibrate the receivers using a first set of phase shift means associated with said plurality of receivers, for relative alignment of the receivers' timing;
• and
• said plurality of receivers is operable to calibrate said drivers using a second set of phase shift means associated with said plurality of drivers, for relative alignment of the drivers' timing.

A method of testing a synchronous semiconductor device, including:

• transmitting a pattern of signals for accessing a set of memory elements within said semiconductor device,
• receiving response signals for detecting failures in the memory elements,
• processing test results, wherein the method further comprises skew calibration comprising:
• calibrating a plurality of output registers of a test header, each of said output registers being connectable to at least one output pin of the semiconductor device in relation to a reference clock edge;
• calibrating propagation delays of a plurality input registers of the test header, each of said input registers being connectable to at least one input pin of the semiconductor device, using the calibrated output registers;
• performing relative alignment of the propagation delays to a main clock edge.

A computer readable medium including a computer readable program means for implementing or simulating hardware functions of a system comprising:

• a plurality of input registers connectable to at least one input pin of a device under test, said input registers latching transmitted signals;
• a plurality of output registers connectable to at least one output pin of said device under test for latching signals received from said device under test;
• a main clock for generating a main clock signal;
• a reference clock for generating a reference signal for calibrating the output registers;
• said reference clock being associated with said main clock;
• a first set of phase shift means associated with said plurality of input registers, for the relative alignment of the input registers' timing;
• and
• a second set of phase shift means associated with said plurality of output registers, for the relative aligment of the output registers' timing.