Methods and apparatus for exploiting virtual buffers to increase instruction parallelism in a pipelined processor

A processor comprising:

• a set of N physical rename registers;
• circuitry for pre-assigning one of said N physical rename registers to an instruction before said one of said N physical rename registers is available to receive a result of said instruction, wherein said pre-assigning circuitry comprises circuitry for assigning M virtual rename buffers to instructions, wherein M is greater than N;
• and
• K architected registers, wherein K≧M.

A processor comprising:

• a set of N physical rename registers;
• circuitry for pre-assigning one of said N physical rename registers to an instruction before said one of said N physical rename registers is available to receive a result of said instruction, wherein said pre-assigning circuitry comprises circuitry for assigning M virtual rename buffers to instructions, wherein M is greater than N;
• and
• K architected registers, wherein N<K≧M.

A processor comprising:

• a set of N physical rename registers;
• circuitry for pre-assigning one of said N physical rename registers to an instruction before said one of said N physical rename registers is available to receive a result of said instruction, wherein said pre-assigning circuitry comprises circuitry for assigning M virtual rename buffers to instructions, wherein M is greater than N;
• and
• K architected registers, wherein K≧N<M.

A method for assigning rename registers, said method comprising the steps of:

• receiving a first instruction where a first result of an execution of said first instruction is to be written to a first architected registers;
• assigning a first virtual rename buffer to correspond to said first architected register, wherein said first virtual rename buffer includes a first pointer to a first physical rename registers, wherein said assigning step is performed whether or not said first physical rename register is available to store said first result;
• receiving a second instruction where a second result of an execution of said second instruction is to be written to a second architected register;
• assigning a second virtual rename buffer to correspond to said second architected register, wherein said second virtual rename buffer includes a second pointer to said first physical rename register;
• determining if said first physical rename register has a first address pointed to by said first pointer;
• executing said first instruction when said first physical rename register has said first address pointed to by said first pointer;
• storing said first result of said execution of said first instruction in said first physical rename register;
• completing said first instruction;
• writing said first result from said first physical rename register to said first architected register;
• transforming said first address into a second address pointed to by said second pointer;
• executing said second instruction;
• storing said second result of said execution of said second instruction in said first physical rename register;
• completing said second instruction;
• and
• writing said second result from said second physical rename register to said second architected register.

A processor comprising:

• an execution unit;
• K architected registers associated with said execution unit;
• N physical rename registers associated with said execution unit;
• M virtual rename buffers, wherein N<M;
• a dispatch unit for receiving a first instruction where a first result of an execution of said first instruction is to be written to a first one of said K architected registers;
• a buffer pointer assignment table for assigning a first one of said M virtual rename buffers to correspond to said first one of said K architected registers, wherein said first one of said M virtual rename buffers includes a first pointer to a first one of said N physical rename registers;
• circuitry for determining if said first one of said N physical rename registers includes a first address corresponding to said first pointer;
• said execution unit executing said first instruction when said first one of said N physical rename registers includes said first address corresponding to said first pointer;
• circuitry for storing said first result of said execution of said first instruction in said first one of said N physical rename registers;
• circuitry for completing said first instruction;
• circuitry for writing said first result from said first one of said N physical rename registers to said first one of said K architected registers;
• said dispatch unit receiving a second instruction where a second result of an execution of said second instruction is to be written to a second one of said K architected registers;
• said buffer pointer assignment table assigning a second one of said M virtual rename buffers to correspond to said second one of said K architected registers, wherein said second one of said M virtual rename buffers includes a second pointer to said first one of said N physical rename registers;
• circuitry for transforming said first address into a second address pointed to by said second pointer;
• said execution unit executing said second instruction;
• and
• circuitry for storing said second result of said execution of said second instruction in said first one of said N physical rename registers.