One-chip microcomputer including RISC processor and one or more coprocessors having control registers mapped as internal registers for the RISC processor

A one-chip microcomputer, comprising:

• a Reduced Instruction Set Computer (RISC) type processor, said RISC type processor being a pipeline processor and including a bypass circuit for generating a flag corresponding to a result of a comparison instruction so that the result of the comparison instruction is available for use in the same pipeline cycle in which the comparison instruction was executed;
• one or more coprocessors coupled to said RISC type processor via a coprocessor bus at least one of said coprocessors having a plurality of general purpose registers and a plurality of control registers, wherein one or more of said control registers are mapped as internal registers for said RISC type processor;
• one or more code buffers for storing instructions used by said microcomputer, said code buffers being coupled to said RISC type processor via an instruction bus;
• and
• one or more data buffers for storing data used by said microcomputer, said data buffers being coupled to said RISC type processor via a data bus;
• wherein said coprocessor bus, said instruction bus and said data bus are distinct buses, and information may be transferred over each of said buses independently;
• and
• wherein said RISC type processor employs multiple purpose instructions formed by adding a plurality of bits to respective fixed-length instructions.