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US 6,298,431 B1Granted
Banked shadowed register file
AssigneeIntel Corporation
InventorRobert Steven Gottlieb
Life of this patent
Estimating the term…
Abstract
An apparatus and method for improving processor performance during multithreaded processing based on the use of a banked shadowed register file for minimizing thread switch overhead.
Claims24
An apparatus, comprising:
- a standard register of a register file coupled to an execution core over a first connection;
- a plurality of shadowed registers to save program thread information;
- an input transmission gate circuit coupled between the standard register and the plurality of shadowed registers over a second connection different than the first connection to transfer first data from the standard register to a first selected one of the plurality of shadowed registers;
- and
- an output transmission gate circuit coupled between the plurality of shadowed registers and the standard register over a third connection different than the first connection to transfer second data from a second selected one of the plurality of shadowed registers to the standard register.
2 more elements
A method, comprising:
- providing a standard register coupled to an execution core over a first connection;
- providing a plurality of supplemental registers coupled to the standard register over a second connection different than the first connection;
- and
- performing a program thread switch in the execution core by:
- transferring a first data from the standard register to a first selected one of the plurality of supplemental registers over the second connection;
- and
- transferring a second data from a second selected one of the plurality of supplemental registers to the standard register over the second connection.
4 more elements
A machine-readable medium having stored thereon instructions, which when executed by at least one processor cause said at least one processor to perform a thread switch in an execution core by:
- transferring a first thread-based state data from a standard register coupled to an execution core to a first selected one of a plurality of supplemental registers over a first connection not coupled to the execution core;
- and
- transferring a second thread-based state data from a second selected one of the plurality of supplemental registers to the standard register over a second connection not coupled to the execution core.
A computer system, comprising:
- a processor having an execution core;
- a memory coupled to the processor;
- a standard register of a register file coupled to the execution core over a first connection;
- a plurality of shadowed registers to save program thread information;
- an input transmission gate circuit coupled between the standard register and the plurality of shadowed registers over a second connection different than the first connection to transfer first data from the standard register to a first selected one of the plurality of shadowed registers;
- and
- an output transmission gate circuit coupled between the plurality of shadowed registers and the standard register over a third connection different than the first connection to transfer second data from a second selected one of the plurality of shadowed registers to the standard register.
4 more elements
Dependencies are inferred from the claim text.