Memory address generator capable of row-major and column-major sweeps

A memory address generation system, comprising:

• an increment/decrement circuit that receives one or more row control signals, one or more column control signals, an increment/decrement control signal, and a current address and generates a generated address, wherein the increment/decrement circuit generates a row address and generates a column address of the generated address in interdependent operations characterized in that a row carry-out signal will affect generation of the column address and a column carry-out signal will affect generation of the row address;
• and
• a storage and initialization circuit that receives the generated address from the increment/decrement circuit, a clock signal, and an initialization control signal, and generates the current address, wherein the storage and initialization circuit temporarily stores the generated address so that the current address is not affected by the generated address from the increment/decrement circuit and wherein the storage and initialization circuit initializes the current address.

A decrement/increment circuit for generating memory addresses, comprising:

• an increment path that generates an increment-generated address given a control signal and a current address, wherein the increment-generated address has a plurality of column bits and a plurality of row bits generated by interdependent operations of the increment Path characterized in that a first row carry-out signal received by the increment path will affect generation of the plurality of column bits of the increment-generated address and a first column carry-out signal received by the increment Path will affect generation of the plurality of row bits of the increment-generated address;
• and
• a decrement path that generates a decrement-generated address given the control signal and the current address, wherein the decrement-generated address has a plurality of column bits and a plurality of row bits generated by interdependent operations of the decrement path characterized in that a second row carry-out signal received by the decrement path will affect generation of the plurality of column bits of the decrement-generated address and a second column carry-out signal received by the decrement path will affect generation of the plurality of row bits of the decrement-generated address.