High performance load/store functional unit and data cache

An apparatus for buffering store information and for providing store forwarding of the store information, the apparatus comprising:

• a first store buffer entry coupled to receive first store information from a store information providing circuit, the first store buffer entry including a first data register circuit, the first data register circuit storing first store data of the first store information and a first address register circuit, the first address register circuit storing the first store address of the first store information, the first store buffer entry including
• a first data register circuit, the first data register circuit storing first store data of the first store information;
• and
• a first tag register circuit, the first tag register circuit storing first tag information of the first store information;
• a second store buffer entry coupled to receive second store information from the store information providing circuit when a second store address does not match a first store address, the second store buffer entry being coupled to receive the second store information from at least one of the store information providing circuit and the first store buffer entry when the second store address matches the first store address, the second store buffer entry including
• a second data register circuit, the second data register circuit storing second store data of the second store information;
• and
• a second tag register circuit, the second tag register circuit storing second tag information of the second store information;
• an address compare circuit coupled to receive store addresses from the store information providing circuit, the address compare circuit causing the first data register circuit to forward the first store data to a load circuit responsive to receiving the first store address from the store information providing circuit while the first store address is stored in the first address register circuit to perform a load forwarding operation;
• and,
• a tag control circuit coupled to receive tag information from the store information providing circuit, the tag control circuit causing the second data register circuit to receive at least a first portion of the second store data from the store information providing circuit, the tag control circuit causing the second data register circuit to receive at least a second portion of the second store data from the first store buffer entry when the second store address matches the first store address and the first tag information matches the tag information received by the tag control circuit from the store information providing circuit,
• wherein
• the second store buffer entry includes a data multiplexer circuit;
• the second store data includes a plurality of data bytes;
• the second tag information includes a plurality of tags, each of the plurality of tags corresponding to a respective one of the plurality of data bytes of the second store data;
• and
• the tag control circuit controls the data multiplexer circuit to select at least one data byte of the second store data from the store information providing circuit for which a corresponding tag matches tag information received by the tag control circuit from the store information providing circuit and to select at least another data byte of the second store data from the first store buffer entry.

An apparatus for buffering store information and for providing store forwarding of the store information, the apparatus comprising:

• a first store buffer entry coupled to receive first store information from a store information providing circuit, the first store buffer entry including a first data register circuit, the first data register circuit storing first store data of the first store information and a first address register circuit, the first address register circuit storing the first store address of the first store information, the first store buffer entry including
• a first data register circuit, the first data register circuit storing first store data of the first store information;
• and
• a first address register circuit, the first address register circuit storing the first store address of the first store information;
• and
• a second store buffer entry coupled to receive second store information from the store information providing circuit when a second store address does not match a first store address, the second store buffer entry being coupled to receive the second store information from at least one of the store information providing circuit and the first store buffer entry when the second store address matches the first store address;
• and,
• an address compare circuit coupled to receive store addresses from the store information providing circuit, the address compare circuit causing the first data register circuit to forward the first store data to a load circuit responsive to receiving the first store address from the store information providing circuit while the first store address is stored in the first address register circuit to perform a load forwarding operation.

An apparatus for buffering store information and for providing store forwarding of the store information, the apparatus comprising:

• a first store buffer entry coupled to receive first store information from a store information providing circuit, the first store buffer entry including a first data register circuit, the first data register circuit storing first store data of the first store information and a first address register circuit, the first address register circuit storing the first store address of the first store information;
• a second store buffer entry coupled to receive second store information from the store information providing circuit when a second store address does not match a first store address, the second store buffer entry being coupled to receive the second store information from at least one of the store information providing circuit and the first store buffer entry when the second store address matches the first store address;
• and,
• an address compare circuit coupled to receive store addresses from the store information providing circuit, the address compare circuit causing the first data register circuit to forward the first store data to a load circuit responsive to receiving the first store address from the store information providing circuit while the first store address is stored in the first address register circuit to perform a load forwarding operation
• wherein the store information providing circuit comprises:
• a merge circuit coupled to receive a number N data bytes from a data cache and N data bytes from a reservation station circuit, the N data bytes from the reservation station circuit including at least one updated data byte, the merge circuit replacing at least one data byte of the N data bytes from the data cache with a corresponding at least one updated data byte from the reservation station circuit to provide N store data bytes including the at least one updated data byte to one of the first and second store buffer entries responsive to receiving the data bytes from the data cache and the reservation station circuit.