Apparatus for controlling refresh of a multibank memory device

A memory controller for controlling operations of a memory having a plurality of banks, comprising:

• a request buffer operable to store a pending data transfer request;
• a refresh requester operable to produce a refresh request;
• and
• a control state machine coupled with the request buffer and with the refresh requester, the control state machine operable to receive the data transfer request and to responsively apply a first plurality of control signals to the memory to initiate data transfer operations thereof, the control state machine also operable to receive the refresh request and to responsively apply a second plurality of control signals to the memory to initiate refresh operations thereof, the control state machine initiating refresh operations addressed to a first of the banks while data transfer operations are being executed in a second of the banks;
• a request arbiter coupling the control state machine with the request buffer and with the refresh requester, the arbiter circuitry operable to determine which of the second data transfer and refresh requests to first provide to the control state machine.

A memory controller for controlling operations of a multibank memory that registers commands and requires a minimum command time interval between successive registration of commands addressed to the same bank, the memory controller comprising:

• request buffer circuitry operable to store a data transfer request;
• refresh request circuitry operable to produce a refresh request;
• and
• control state circuitry coupled with the request buffer circuitry and with the refresh request circuitry, the control state circuitry operable to receive the data transfer request and to responsively register a data transfer command in the memory, the control state circuitry also operable to receive the refresh request and to responsively register a refresh command in the memory prior to elapse of the command time interval from registration of the data transfer command to initiate a refresh operation directed to a first memory bank while a data transfer operation is being executed in a second memory bank.

A memory controller for controlling operations of a memory having a plurality of banks, comprising:

• a request buffer operable to store a pending data transfer request;
• a refresh requester operable to produce a refresh request;
• a request arbiter coupled with the request buffer and with the refresh requester to receive the data transfer and refresh requests, the arbiter circuitry operable to determine the order in which the data transfer requests and the refresh requests are executed;
• and
• a control state machine coupled with the request arbiter, the control state machine operable to receive the data transfer request from the request arbiter and to responsively apply a first plurality of control signals to the memory to initiate data transfer operations thereof, the control state machine also operable to receive the refresh request from the request arbiter and to responsively apply a second plurality of control signals to the memory to initiate refresh operations thereof, the control state machine initiating refresh operations addressed to a first of the banks while data transfer operations are being executed in a second of the banks.

A memory controller for controlling operations of a multibank memory that registers commands and requires a minimum command time interval between successive registration of commands aessed to the same bank, the memory controller comprising:

• request buffer circuitry operable to store a data transfer request;
• refresh request circuitry operable to produce a refresh request;
• control static circuitry operable to receive the data transfer request and to responsively register a data transfer command in the memory, the control state circuitry also operable to receive the refresh request and to responsively register a refresh command in the memory prior to elapse of the command time interval from registration of the data transfer command;
• and
• arbiter circuitry coupling the control state circuitry with the request buffer circuitry and with the refresh request circuitry to provide the control state circuitry data transfer requests and refresh request, the arbiter circuitry operable to determine the order in which to provide data transfer and refresh requests to the control state circuitry to initiate a refresh operation directed to a first memory bank while a data transfer operation is being executed in a second memory bank.