Apparatus and method for initiating hardware priority management by software controlled register access

A register-based interrupt controller comprising:

• an interrupt vector register for holding an interrupt vector;
• and
• an interrupt logic circuit coupled to said interrupt vector register for performing a hardware interrupt sequence when an interrupt is to be processed by software, the hardware interrupt sequence is initiated when the software performs a read to said interrupt vector register, in which said interrupt logic circuit determines interrupt priority and returns a vector of a highest priority to said interrupt vector register, wherein said interrupt logic circuit determines if a non-maskable interrupt is present and if the non-maskable interrupt is present, returning the non-maskable interrupt to said interrupt vector register;
• else if the non-maskable interrupt is not present, then said interrupt logic circuit determines if interrupts have not been disabled or if an interrupt having the highest priority is not being serviced, and returning a vector corresponding to the highest priority interrupt to said interrupt vector register.

A programmable interrupt controller for controlling interrupts in a computer comprising:

• an interrupt vector register for holding an interrupt vector;
• and
• an interrupt logic circuit coupled to said interrupt vector register for performing a hardware interrupt sequence when an interrupt is to be processed by software, the hardware interrupt sequence is initiated when the software performs a read to said interrupt vector register, in which said interrupt logic circuit determines interrupt priority and returns a prioritized vector to said interrupt vector register, wherein said interrupt logic circuit determines if a non-maskable interrupt is present and if the non-maskable interrupt is present, returning the non-maskable interrupt to said interrupt vector register;
• else if the non-maskable interrupt is not present, then said interrupt logic circuit determines if interrupts have not been disabled or if an interrupt having a selected priority is not being serviced, and returning a vector corresponding to the selected priority interrupt to said interrupt vector register.

In a processing device, a programmable interrupt controller comprising:

• an interrupt vector register for holding an interrupt vector;
• an interrupt logic circuit coupled to said interrupt vector register for performing a hardware interrupt sequence when an interrupt is to be processed by software, the hardware interrupt sequence is initiated when the software performs a read to said interrupt registers, in which said interrupt logic circuit determines interrupt priority and returns a prioritized vector to said interrupt vector register;
• an interrupt service register for storing therein a vector of an interrupt being service;
• and
• an interrupt request register coupled to said interrupt vector register and said interrupt service register and having stored therein priority associated with pending interrupts.

A method for controlling interrupts in a computer comprising:

• determining if a non-maskable interrupt is present;
• returning in an interrupt vector register a non-maskable interrupt when the interrupt vector register is read by programmable software, if the non-maskable interrupt is present;
• if a non-maskable interrupt is not present, but if interrupts have been disabled or if an interrupt having highest priority is being serviced, returning in the interrupt vector register a first vector when the interrupt vector register is read by the programmable software;
• and
• if a non-maskable interrupt is not present, and if interrupts have not been disabled or if the interrupt having highest priority is not being serviced, returning in the interrupt vector register a vector for the interrupt having highest priority when the interrupt vector register is read by the programmable software.

A method for control of interrupts in a computer, comprising:

• triggering control action by having software read an interrupt vector register;
• determining if a non-maskable interrupt is present;
• returning to the interrupt vector register the non-maskable interrupt, if a non-maskable interrupt is present;
• returning to the interrupt vector register a first vector, if a non-maskable interrupt is not present, and if interrupts are disabled, or if a value in a highest pending interrupt register is less than, or equal to, a value in a highest servicing interrupt register;
• sending an interrupt service register bit corresponding to a top-most vector in an interrupt request registers and returning to the interrupt vector register the top-most vector in the interrupt request register, if a non-maskable interrupt is not present, and if a task priority register has not disabled interrupts, and if a value in the highest pending interrupt register is greater than a value in the highest servicing interrupt register.