Trigger points for performance optimization in bus-to-bus bridges
AssigneeIntel Corporation
InventorsBarry R. Davis, Nick G. Eskandari
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AssigneeIntel Corporation
InventorsBarry R. Davis, Nick G. Eskandari
Estimating the term…
Method and apparatus for tuning the performance of bridge devices, including PCI-to-PCI bridges as well as PCI local bus bridges (or host bridges). The embodiments of the invention permit a multiple-bus computer system to be tuned in view of the application and the bridge queue sizes. Such applications include those concerned with raw bandwidth (such as disk storage), and those that are sensitive to latency (such as networking and videoconferencing). The embodiments of the invention feature a control register that specifies storage conditions to be met by the read and write queues of the bridge. The programmed storage conditions are trigger points which cause the bridge to transfer data into or remove data from the queues during read and write transactions in order to promote the performance (throughput or latency) desired from the bridge.
An apparatus comprising:
A bridge comprising:
In a bridge coupling an initiating bus to a target bus through a data buffer, a method comprising:
In a bridge coupling an initiating bus to a target bus through a data buffer, a method comprising:
In a bridge coupling an initiator on an initiating bus to a target on a target bus through a data buffer, a method comprising:
An apparatus comprising:
An apparatus comprising:
Dependencies are inferred from the claim text.