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AssigneeRicoh Company, Ltd.
InventorTeruyuki Maruyama
Estimating the term…
It is determined that, when starting of direct memory access is newly requested, whether or not the direct memory access can be started, using a rate of using the bus at the present time by data transfer performed by all the direct memory access controllers which have already started direct memory access until then and all the processors, a data transfer rate needed by the newly requested direct memory access, a size of data which is transferred in one direct memory access operation or a size of data which a memory can accept, a latency for accessing the memory, and a latency for bus-right arbitration. The newly requested direct memory access is started when it is determined that the direct memory access can be started. Starting of the newly requested direct memory access is kept waiting when it is determined that the direct memory access cannot be started. The newly requested direct memory access, which has been kept waiting, is started when any direct memory access which has already been carried out finishes, and enough capacity is free in the common bus for carrying out the newly requested direct memory access.
A data transfer control system, comprising:
A data transfer control method for use in a system including a common bus, at least one processor connected to said common bus, at least one direct memory access controller connected to said common bus and a memory connected to said common bus, said method comprising:
A computer program product comprising a computer storage medium having a computer program code mechanism embedded in said computer storage medium for causing a computer to perform data transfer control in a system including a common bus, at least one processor connected to said common bus, at least one direct memory access controller connected to said common bus and a memory connected to said common bus, said computer program code mechanism comprising:
Dependencies are inferred from the claim text.