Floating point addition pipeline including extreme value, comparison and accumulate functions

A microprocessor comprising:

• an execution unit coupled to receive a first set of input data values, a second set of input data values, and an instruction indication specifying an operation to be performed by said execution unit, wherein said execution unit includes:
• an input multiplexer unit coupled to receive said first set of input data values, said second set of input data values, and said instruction indication, wherein said input multiplexer is configured to select a first set of operands and a second set of operands from said first pair of input data values and said second pair of input data values in response to said instruction indication;
• a first add/subtract pipeline coupled to receive said first set of operands and said instruction indication, wherein said first add/subtract pipeline is configured to generate a first result value from said first set of operands by performing an arithmetic operation specified by said instruction indication;
• a second add/subtract pipeline coupled to receive said second set of operands and said instruction indication, wherein said second add/subtract pipeline is configured to generate a second result value from said second set of operands by performing said arithmetic operation specified by said instruction indication;
• wherein said first result value and said second result value are generated concurrently, wherein said first pair of input data values includes a first floating point number, and wherein said second pair of input data values includes a second floating point number, wherein said input multiplexer unit is configured to select said first set of operands to include said first floating point number in response to said instruction indication specifying a floating point to integer conversion operation, and wherein said input multiplexer unit is configured to select said second set of operands to include said second floating point number in response to said instruction indication specifying said floating point-to-integer conversion operation.

A microprocessor, comprising:

• a means for receiving a first set of input data values, a second set of input data values, and an instruction indication, wherein said means for receiving is configured to select a first set of operands and a second set of operands from said first pair of input data values and said second pair of input data values in response to said instruction indication;
• a first add/subtract means coupled to receive said first set of operands and said instruction indication, wherein said first add/subtract means is configured to generate a first result value from said first set of operands by performing an arithmetic operation specified by said instruction indication;
• a second add/subtract means coupled to receive said second set of operands and said instruction indication, wherein said second add/subtract means is configured to generate a second result value from said second set of operands by performing said arithmetic operation specified by said instruction indication;
• wherein said first pair of input data values includes a first floating point number, and wherein said second pair of input data values includes a second floating point number, wherein said means for receiving is configured to select said first set of operands to include said first floating point number in response to said instruction indication specifying a floating point to integer conversion operation, and wherein said means for receiving is configured to select said second set of operands to include said second floating point number in response to said instruction indication specifying said floating point-to-integer conversion operation.