Clock recovery circuit

Abstract

A clock recovery circuit enables a time for obtaining synchronized state of one pair of gate voltage-controlled oscillator to be shortened in a phase locked loop (PLL). In the clock recovery circuit, data is inputted to a pulse-duration generating circuit, before generating pulse width less than ¼ minimum data cycle from H of pulse, L of pulse, or both edges of H and L, thus the pulse is outputted both to a latched-circuit and a synchronous delay circuit. The synchronous delay circuit causes a delay time in proportion to data cycle to be generated at both edges of pulse or edge of two pulses, thus the delay time is maintained. An output pulse from a delay circuit is outputted both to a delay circuit and a latched-circuit by way of clock from the pulse synthesis circuit. The latched-circuit causes the data as an input to be latched by the clock from the pulse synthesis circuit, thus outputting regenerative data in company with the clock.

Dependencies are inferred from the claim text.