Method and apparatus for eliminating false data in a page mode memory device
AssigneesAdvanced Micro Device, Inc., Fujitsu Limited
InventorsVikram S. Santurkar, Yasushi Kasa
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Abstract
A flash memory (100) includes a core cell array (104), address decoders (116), one or more output buffers (110) and sensing circuitry including sense amplifiers which sense data at an address selected by the address decoders. A data switching multiplexer (108) is coupled to the output buffers to select a sense amplifier for a current word of data in response to a control signal (RWDEN) . A control circuit (106) is coupled to the data switching multiplexer to provide the control signal at a time to ensure the current word of data is provided to the output buffers.
Claims15
A memory circuit comprising a core cell;
- a sense amplifier coupled to said core cell;
- a redundant core cell;
- a redundant sense amplifier coupled to said redundant core cell;
- an output buffer coupled to said sense amplifier and said redundant core cell;
- an address transition detector producing a signal in response to an input address signal bit;
- and a delay circuit coupled to said address transition detector thereby producing a delayed control signal;
- wherein sensed data from said sense amplifier and said redundant sense amplifier are passed to said output buffer in response to said delayed control signal.
A memory circuit comprising means for storing data;
- means for sensing said storage means;
- means for detecting faulty data storage means and replacing said storage means with redundant storage means;
- means for sensing said redundant storage means;
- means for outputting said sensed storage means and said redundant storage means;
- means for receiving an address signal;
- and means for delaying said means for outputting after a transition in said address signal thereby allowing correct data to be output and preventing faulty data from being output.
A method for outputting data from a memory circuit in a page mode comprising receiving an input address signal;
- detecting a transition in said input address signal;
- generating a delayed control signal in response to said transition detection;
- sensing a core cell;
- sensing a redundant core cell;
- and passing data from said sensed core cell and said redundant core cell in response to said delayed control signal thereby perventing old data from being output.
Dependencies are inferred from the claim text.