Semiconductor memory device and method for setting stress voltage

A semiconductor memory device comprising:

• a plurality of words lines;
• pairs of bit lines intersecting the word lines;
• a plurality of memory cells located at the intersections between the word lines and the pairs of bit lines;
• a plurality of sense amplifiers, each connected to one of the pairs of bit lines for amplifying a potential difference between the associated pair of bit lines;
• a plurality of column gates, each connected to one of the pairs of bit lines;
• a plurality of data buses connected via the column gates to the pairs of bit lines;
• and
• a burn-in test control circuit for providing a stress voltage to the word lines and the pairs of bit lines so to perform a burn-in test based on a burn-in control signal, wherein the burn-in test control circuit includes:
• a potential generation circuit connected to the plurality of data buses for generating a potential difference between the plurality of data buses based on the burn-in control signal;
• and
• a column decoder connected to the column gates to connect the plurality of data buses to the pairs of bit lines based on the burn-in control signal, wherein each of the sense amplifiers amplifies the potential difference to provide the stress voltage between the plurality of word lines and the associated pair of bit lines and between the associated pair of bit lines.

A semiconductor memory device comprising:

• a plurality of words lines;
• pairs of bit lines intersecting the word lines;
• a plurality of memory cells located at the intersections between the word lines and the pairs of bit lines;
• a plurality of sense amplifiers, each connected to one of the pairs of bit lines for amplifying a potential difference between the associated pair of bit lines, wherein each of the sense amplifiers includes a pair of input nodes;
• plural sets of bit line separation switches, each connected between the associated pair of bit lines and the pair of input nodes of the associated sense amplifier;
• and
• a burn-in test control circuit for providing a stress voltage to the plurality of word lines and the pairs of bit lines to perform a burn-in test based on a burn-in control signal, wherein the burn-in test control circuit includes a switch control circuit for selectively activating one set of the bit line separation switches associated with one of the pairs of bit lines based on the burn-in control signal before selection of the word lines, so to produce a potential difference between the input nodes of the sense amplifier associated with the set of the bit line separation switches.

A method for setting a stress voltage applied to a semiconductor memory device, wherein the semiconductor memory device includes a plurality of word lines, pairs of bit lines intersecting the word lines, a plurality of dummy word lines intersecting the pairs of bit lines, and a plurality of sense amplifiers each connected to one of the pairs of bit lines for amplifying a potential difference between the associated pair of bit lines, the method comprising the steps of:

• selecting at least one of the dummy word lines;
• producing a potential difference between at least one of the pairs of bit lines;
• amplifying the potential difference by activating the sense amplifier associated with the at least one of the pairs of bit lines;
• selecting all of the word lines;
• and
• providing a stress voltage between all of the word lines and the at least one of the pairs of bit lines and between the at least one of the pairs of bit lines.

A method for setting a stress voltage applied to a semiconductor memory device, wherein the semiconductor memory device includes a plurality of word lines, pairs of bit lines intersecting the word lines, a plurality of dummy word lines intersecting the pairs of bit lines, a plurality of sense amplifiers each connected to one of the pairs of bit lines for amplifying a potential difference between the associated pair of bit lines, and a pair of data buses connected via the column gates to the pairs of bit lines, the method comprising the steps of:

• generating a potential difference between the pair of data buses;
• providing the potential difference to the pairs of bit lines by connecting the pair of data buses to the pairs of bit lines;
• amplifying the potential difference by activating the sense amplifiers;
• selecting all of the word lines;
• and
• providing a stress voltage between all of the word lines and the pairs of bit lines and between the pairs of bit lines.

A method for setting a stress voltage applied to a semiconductor memory device, wherein the semiconductor memory device includes a plurality of word lines, pairs of bit lines intersecting the word lines, a plurality of dummy word lines intersecting the pairs of bit lines, a plurality of sense amplifiers each having a pair of input nodes and connected to one of the pairs of bit lines for amplifying a potential difference between the associated pair of bit lines, and plural sets of bit line separation switches each connected to one of the pairs of bit lines and to the pair of input nodes of the associated sense amplifier, the method comprising:

• activating one set of the bit line separation switches associated with one of the pairs of bit lines to produce a potential difference between the pair of the input nodes of the sense amplifier associated with the one set of the bit line separation switches;
• selecting all of the word lines;
• amplifying the potential difference by activating the sense amplifier associated with the one set of the bit line separation switches;
• and
• providing a stress voltage between all of the word lines and one of the pairs of bit lines and between the pairs of bit lines by activating the one set of the bit line separation switches.