Semiconductor device capable of reducing cost of analysis for finding replacement address in memory array
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsJun Ohtani, Mitsuhiro Hamada
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Abstract
In a semiconductor device including banks A and B, testing and redundancy analysis of the bank B are first carried out by using a conventional tester, and redundancy replacement is carried out. Then, the bank A is tested by a BIST circuit and the test result of each bit is written to the bank B. By using the bank B as a memory for defect analysis, a tester connected to the semiconductor device while testing the bank A does not need a large capacity analysis memory. Thus, an inexpensive redundancy analysis system can be provided.
Claims13
A semiconductor device, comprising:
- (a) first and second memory regions carrying out a storing operation to hold applied data,
- said first and second memory regions each including
- (a-1) a plurality of normal memory cells arranged in rows and columns,
- (a-2) a spare row replacing a normal row including a defective memory cell in said plurality of normal memory cells, and
- (a-3) a spare column replacing a normal column including a defective memory cell in said plurality of normal memory cells;
- and
- (b) a memory control circuit controlling operation of said first and second memory regions according to a designated operation mode,
- said memory control circuit including
- (b-1) a self test circuit inactivated when said operation mode is a normal mode, and generating test data to be written to said first memory region, reading data held in said first memory region after said test data is written and determining whether or not a memory cell is good according to a comparison result of a read value and an expected value when said operation mode is a test mode, and
- (b-2) a data transfer circuit transmitting said test data to said first memory region and transferring said comparison result to said second memory region in said test mode.
A method of testing a semiconductor device including first and second memory banks, a replacement circuit repairing a defective bit in said first and second memory banks, a self test circuit, and a data transfer circuit, comprising the steps of:
- testing said second memory bank and repairing a defective memory cell included in said second memory bank by using said replacement circuit;
- testing said first memory bank by using said self test circuit and writing a test result to said second memory bank through said data transfer circuit;
- and
- reading said test result written in said second memory bank and finding a row address and a column address corresponding to a normal row and a normal column to be replaced by a spare row and a spare column.
Dependencies are inferred from the claim text.