US 6,297,986 B1Granted

Ferroelectric random access memory

AssigneeDongbu Electronics Co., Ltd.

InventorKim Jae Kap

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Abstract

Disclosed is a ferroelectric random access memory including a plurality of bit lines extending in one direction, a plurality of plate electrode lines extending in another direction perpendicular to the one direction, a plurality of word lines extending in the same direction as the plate electrode lines, and a plurality of unit cells arranged in an M×N array. The unit cells are grouped into a plurality of unit cell groups, each unit cell group consists of a plurality of unit cells connected to associated bit lines such that the unit cells are interlaced in a row direction or in a column direction. A dummy cell group consists of a plurality of dummy cells each connected to an associated one of the bit lines at an optional position on the associated bit line. A switching transistor group consists of a plurality of switching transistors each serving to switch a connection between associated ones of the unit cells on an associated one of the bit lines, and to switch an input-to-input/output-to-output coupling between two associated dummy cells, in response to a control signal externally applied. When data is read from an optional one of the unit cells on a selected one of the bit lines, an average voltage between voltages respectively outputted from those of the dummy cells connected to two bit lines neighboring to the selected bit line is applied to the neighboring bit lines as a reference voltage required for a comparison with a voltage corresponding to the read-out data.

Claims31

Dependent claims

A ferroelectric random access memory comprising a plurality of bit lines extending in one direction, a plurality of plate electrode lines extending in another direction perpendicular to the one direction, a plurality of word lines extending in the same direction as the plate electrode lines, and a plurality of unit cells arranged in an M×N array while being connected to associated ones of the lines, each of the unit cells consisting of one transistor and one capacitor,

wherein the unit cells are grouped into a plurality of unit cell groups, each of the unit cell groups consisting of a plurality of unit cells connected to associated ones of the bit lines, respectively, in such a fashion that they are arranged in an interlaced fashion in a row direction or in a column direction, those of the bit lines connected to each of the bit lines being connected together in series;
further comprising:
a dummy cell group consisting of a plurality of dummy cells each connected to an associated one of the bit lines at an optional position on the associated bit line, each of the dummy cells consisting of one transistor and one capacitor;
and
a switching transistor group consisting of a plurality of switching transistors each serving to switch a connection between associated ones of the unit cells on an associated one of the bit lines, and to switch an input-to-input/output-to-output coupling between two associated ones of the dummy cells, in response to a control signal externally applied thereto;
whereby when data is read out from an optional one of the unit cells one a selected on of the bit lines, an average voltage between voltages respectively outputted from those of the dummy cells connected to two bit lines neighboring to the selected bit line is applied to the neighboring bit lines as a reference voltage required for a comparison with a voltage corresponding to the read-out data.

3 more elements

A ferroelectric random access memory comprising a plurality of bit lines extending in one direction, a plurality of word lines in another direction perpendicular to the one direction, and a plurality of unit cells arranged in an M×N array while being connected to associated ones of the lines, each of the unit cells consisting of one transistor and one capacitor,

wherein the unit cells are grouped into a plurality of unit cell groups, each of the unit cell groups consisting of a plurality of unit cells connected to associated ones of the bit lines, respectively, in such a fashion that they are arranged in an interlaced fashion in a row direction or in a column direction, those of the bit lines connected to each of the bit lines being connected together in series;
further comprising:
a dummy cell group consisting of a plurality of dummy cells each connected to an associated one of the bit lines at an optional position on the associated bit line, each of the dummy cells consisting of one transistor and one capacitor;
a switching transistor group consisting of a plurality of switching transistors each serving to switch a connection between associated ones of the unit cells on an associated one of the bit lines, and to switch an input-to-input/output-to-output coupling between two associated ones of the dummy cells, in response to a control signal externally applied thereto;
a common plate electrode line, to which respective plate electrodes of the unit cells and respective plate electrodes of the dummy cells are connected in common, the common plate electrode line being applied with a predetermined voltage;
whereby when data is read out from an optional one of the unit cells on a selected one of the bit lines, an average voltage between voltages respectively outputted from those of the dummy cells connected to two bit lines neighboring to the selected bit line is applied to the neighboring bit lines as a reference voltage required for a comparison with a voltage corresponding to the read-out data.

3 more elements

wherein the unit cells are grouped into a plurality of unit cell groups, each of the unit cell groups consisting of a plurality of unit cells connected to associated ones of the bit lines, respectively, in such a fashion that they are arranged in an interlaced fashion in a row direction or in a column direction, those of the bit lines connected to each of the bit lines being connected together in series;
further comprising:
a dummy cell group consisting of a plurality of dummy cells each connected to an associated one of the bit lines at an optional position on the associated bit line, each of the dummy cells consisting of one transistor and one capacitor;
a switching transistor group consisting of a plurality of switching transistors each serving to switch an input-to-input/output-to-output coupling between respective dummy cells connected to two of the bit lines neighboring to each other in an interlaced fashion, the switching transistor applying an output thereof to a selected one of the two neighboring bit lines in response to a control signal externally applied thereto;
a common plate electrode line, to which respective plate electrodes of the unit cells and respective plate electrodes of the dummy cells are connected in common, the common plate electrode line being applied with a predetermined voltage;
whereby when data is read out from an optional one of the unit cells on a selected one of the bit lines, an average voltage between voltages respectively outputted from those of the dummy cells connected to two bit lines neighboring to the selected bit line is applied to the neighboring bit lines as a reference voltage required for a comparison with a voltage corresponding to the read-out data.

3 more elements

Dependencies are inferred from the claim text.