Method and apparatus for reducing stress across capacitors used in integrated circuits

In a charge pump having a plurality of pump stages connected in series, at least one of the pump stages including at least one node to be coupled to a corresponding clock signal via a capacitive device, the at least one node having a first voltage when the charge pump is in a first power state and a second voltage when the charge pump is in a second power state, a method of balancing the voltage requirement at the at least one node with the stress limitation and die area of the capacitive device, the method comprising:

• using a single capacitor of a first type as the capacitive device between the at least one node and the corresponding clock signal if the first voltage and second voltage do not exceed the stress limitation of the single capacitor of the first type;
• if the second voltage exceeds the stress limitation of the single capacitor of the first type, using a single capacitor of a second type as the capacitive device between the at least one node and the corresponding clock signal if the first voltage and second voltage do not exceed the stress limitation of the single capacitor of the second type, the single capacitor of the second type having greater stress limitation and greater die area than the single capacitor of the first type;
• and
• if the second voltage exceeds the stress limitation of the single capacitor of the second type, using two capacitors of the first type connected in series as the capacitive device between the at least one node and the corresponding clock signal if the first voltage and second voltage do not exceed the combined stress limitation of the two capacitors of the first type;
• and
• if the first voltage exceeds the combined stress limitation of the two capacitors of the first type, setting the middle node between the two capacitors of the first type to a third voltage level when the charge pump is in the first power state such that the voltage across each of the two capacitors does not exceed the stress limitation of the respective capacitor, the third voltage level at the middle node corresponds to the voltage level at the first node when the charge pump is placed in the first power state.

A charge pump circuit including a plurality of pump stages being connected in series each having an input node and an output node, at least one of the pump stages comprising:

• a switching transistor having a gate, a first terminal, and a second terminal, the first terminal being coupled to the input node of the respective pump stage and the second terminal being coupled to the output node of the respective pump stage;
• a first capacitor having a first end and a second end, the first end of the first capacitor being coupled to the gate of the switching transistor;
• a second capacitor having a first end and a second end, the first end of the second capacitor being coupled to the second end of the first capacitor forming a first intermediate node, the second end of the second capacitor being coupled to a first clock signal;
• a third capacitor having a first end and a second end, the first end of the third capacitor being coupled to the output node of the respective pump stage;
• and
• a fourth capacitor having a first end and a second end, the first end of the fourth capacitor being coupled to the first end of the third capacitor forming a second intermediate node, the second end of the fourth capacitor being coupled to a second clock signal
• wherein the first and second intermediate nodes are set to a predetermined voltage level when the charge pump circuit is placed in a low power state.

A charge pump stage in a charge pump circuit, the charge pump stage comprising:

• a first switching transistor having a gate, a first terminal and a second terminal, the first terminal being coupled to an input node of the charge pump stage, the second terminal being coupled to an output node of the charge pump stage;
• at least two capacitors connected in series between the gate of the first switching transistor and a first clock signal forming a first intermediate node between the two capacitors;
• at least two capacitors connected in series between the output node and a second clock signal forming a second intermediate node between the two capacitors;
• a control device to connect the first and second intermediate nodes to a first voltage source when the charge pump circuit is in a first power state and to disconnect the first and second intermediate nodes from the first voltage source when the charge pump circuit is in a second power state;
• a first diode having an input terminal and an output terminal, the input terminal being coupled to the first terminal of the first switching transistor and the output terminal being coupled to the gate of the first switching transistor;
• and
• a second diode having an input terminal and an output terminal, the input terminal being coupled to the gate of the first transistor, the output terminal being coupled to the first terminal of the first switching transistor.