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US 6,297,705 B1Granted
Circuit for locking an oscillator to a data stream
AssigneeCypress Semiconductor Corporation
InventorsTimothy J. Williams, Jeffrey D. Wick
Life of this patent
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Abstract
An apparatus comprising a control circuit and a first circuit. The first circuit may be configured to generate a calibration signal in response to an adjustment signal and a first control signal. The control circuit may be configured to generate (i) the first control signal, (ii) a second control signal and (iii) the adjustment signal in response to a rate of an input signal.
Claims19
The apparatus comprises:
- a first circuit comprising one or more counters, said first circuit configured to generate a calibration signal and an output signal in response to an adjustment signal and a first control signal;
- and
- a control circuit configured to generate (i) said first control signal, (ii) a second control signal and (iii) said adjustment signal in response to a rate of an input signal.
The apparatus comprises:
- a first circuit configured to generate a calibration signal in response to (i) a coarse/fine adjustment signal and (ii) a first control signal;
- and
- a control circuit configured to generate (i) said first control signal, (ii) a second control signal and (iii) said adjustment signal in response to a rate of an input signal.
An apparatus comprising:
- an oscillator circuit configured to generate a clock signal in response to a first control signal and a calibration signal;
- and
- a first circuit configured to generate said calibration signal and said control signal in response to a rate of an input signal, wherein said first circuit comprises (a) a counter circuit configured to generate said calibration signal in response to an adjustment signal and a second control signal and (b) a control circuit configured to generate (i) said first control signal, (ii) said second control signal and (iii) said adjustment signal in response to a rate of an input signal.
A method for locking a clock signal to a rate of a data stream comprising the steps of:
- (A) generating a multi-bit word;
- (B) generating said clock signal in response to a first control signal, a calibration signal and said multi-bit digital word;
- and
- (C) generating said calibration signal and said first control signal in response to a rate of an input signal.
1 more element
Dependencies are inferred from the claim text.