Circuit and method for switching between digital signals that have different signal rates

A method of switching between signals having signal rates that differ, the method using a control signal having a plurality of transitions between a first state and a second state, the method comprising:

• receiving a first digital signal having a first signal rate, wherein the first digital signal is a data signal conforming to IEEE Standard 1394;
• receiving a second digital signal having a second signal rate that differs from the first signal rate, wherein the second digital signal is an arbitration signal conforming to IEEE Standard 1394;
• receiving the control signal in one of the transitions between states, and in response:
• supplying an output signal responsive to both the first and the second digital signal for an interval of time;
• and then
• supplying the output signal responsive to exactly one of the first and second digital signals.

A method of switching between signals having signal rates that differ, the method using a control signal having a plurality of transitions between a first state and a second state, the method comprising:

• receiving a first digital signal having a first signal rate, wherein the first digital signal is a strobe signal conforming to IEEE Standard 1394;
• receiving a second digital signal having a second signal rate that differs from the first signal rate, wherein the second digital signal is an arbitration signal conforming to IEEE Standard 1394;
• receiving the control signal in one of the transitions between states, and in response:
• supplying an output signal responsive to both the first and the second digital signal for an interval of time;
• and then
• supplying the output signal responsive to exactly one of the first and second digital signals.

A method of switching between signals having signal rates that differ, the method using a control signal having a plurality of transitions between a first state and a second state, the method comprising:

• receiving a first digital signal having a first signal rate;
• receiving a second digital signal having a second signal rate that differs from the first signal rate;
• receiving the control signal in one of the transitions between states, and in response:
• supplying a first output signal responsive to both the first and the second digital signal for an interval of time;
• and then
• supplying a second output signal responsive to exactly one of the first and second digital signals;
• wherein the first and second output signals are supplied to a common conductive line.

A multiplexor comprising:

• a first signal-transfer circuit having a first input node for receiving a first input signal, a first intermediate output node, and a first enable input terminal, said first signal-transfer circuit being effective for coupling said first input node to said first intermediate output node in response to assertion of a first enable signal at said first enable input terminal whereby said first input signal is transferred to said first intermediate output node, and effective for isolating said first input node from said first intermediate output node in response to said first enable signal not being asserted at said first enable terminal whereby said first input signal is not transferred to said first intermediate output node;
• a second signal-transfer circuit having a second input node for receiving a second digital input signal, a second intermediate output node, and a second enable input terminal, said second signal-transfer circuit being effective for coupling said second input node to said second intermediate output node in response to assertion of a second enable signal at said second enable input terminal whereby said second input signal is transferred to said second intermediate output node, and effective for isolating said second input node from said second intermediate output node in response to said second enable signal not being asserted at said second enable input terminal whereby said second input signal is isolated from said second intermediate output node;
• a controller having a control input node for receiving a selection signal for selecting one of said first and second signal-transfer circuits, a first enable output node for asserting said first enable signal at said first enable input terminal in response to said selection signal selecting said first signal-transfer circuit, and a second enable output node for asserting said second enable signal at said second enable input terminal in response to said selection signal selecting said second signal-transfer circuit, said controller responding to said selection signal switching its selection from said first signal-transfer circuit to said second signal-transfer, circuit by concurrently asserting both of said first and second enable signals for a first predetermined delay period and then deasserting said first enable signal while continuing to assert said second enable signal, said controller responding to said selection signal switching its selection from said second signal-transfer circuit to said first signal-transfer circuit by concurrently asserting both of said first and second enable signals for a second predetermined delay period and then deasserting said second enable signal while continuing to assert said first enable signal;
• a multiplexor output node coupled to said first and second intermediate output nodes for supplying a multiplexor output signal.

A multiplexor for switching between a first and a second digital signal in response to a control signal, the control signal having a first state and a second state, the multiplexor comprising:

• a controller having an input for receiving the control signal, a first controller output that asserts the first state during a first interval of time that begins substantially when the control signal attains the first state and ends after the control signal remains in the second state for a second interval of time, and a second controller output that asserts the second state during a third interval of time that begins substantially when the control signal attains the second state and ends after the control signal remains in the first state for a fourth interval of time;
• a first switch having an input for receiving the first digital signal, a control terminal coupled to the first controller output of the controller, and an output for supplying a first intermediate signal representing the first digital signal while said first controller output asserts the first state;
• a second switch having an input for receiving the second digital signal, a control terminal coupled to the second controller output of the controller, and an output for supplying a second intermediate signal representing the second digital signal while said second controller output asserts the second state;
• a multiplexor output coupled to the outputs of the first and second switches for supplying an output signal;
• wherein the output signal switches from being responsive to the first intermediate signal, to being responsive to a logical OR of the first and second intermediate signals, to being responsive to the second intermediate signal.

A multiplexor for switching between a first and a second digital signal in response to a control signal, the control signal having a first state and a second state, the multiplexor comprising:

• a controller having an input for receiving the control signal, a first controller output that asserts the first state during a first interval of time that begins substantially when the control signal attains the first state and ends after the control signal remains in the second state for a second interval of time, and a second controller output that asserts the second state during a third interval of time that begins substantially when the control signal attains the second state and ends after the control signal remains in the first state for a fourth interval of time;
• a first switch having an input for receiving the first digital signal, a control terminal coupled to the first controller output of the controller, and an output for supplying a first intermediate signal representing the first digital signal while said first controller output asserts the first state;
• a second switch having an input for receiving the second digital signal, a control terminal coupled to the second controller output of the controller, and an output for supplying a second intermediate signal representing the second digital signal while said second controller output asserts the second state;
• a multiplexor output coupled to the outputs of the first and second switches for supplying an output signal;
• wherein the second interval of time is selected relative to a signal rate differential between the first and second digital signals to prevent glitches due to such signal rate differential from arising in the output signal.

A multiplexor comprising:

• a first input node for receiving a first input signal;
• a second input node for receiving a second input signal;
• a transition control circuit having a control input for selecting one of said first and second input nodes, a first output select node for issuing a first selection signal in response to said control input selecting said first input node, and a second output select node for issuing a second selection signal in response to said control input selecting said second input node;
• said transition control circuit being further effective for simultaneously issuing both of said first and second selection signals for a predetermined period in response to said control input transitioning its selection from one of said first and second input nodes to the other;
• an output control circuit having a multiplexer output node, said output control circuit being effective for coupling said first input node to said multiplexer output node while maintaining said second input node isolated from said multiplexer output node in response to said transition control circuit issuing said first selection signal and not issuing said second selection signal;
• said output control circuit being also effective for coupling said second input node to said multiplexer output node while maintaining said first input node isolated from said multiplexer output node in response to said transition control circuit issuing said second selection signal and not issuing said first selection signal:
• said output control circuit being further effective for logically combining said first and second input signals and outputting a resultant signal on said multiplexer output node in response to said transition control circuit simultaneously issuing said first and second selection signals.

A method for switching a multiplexor, the multiplexor including a first input, second input, an output, and a control terminal for selectively switching the coupling of said first and second inputs to said output, said method comprising the following steps:

• a. supplying said first input with a first digital signal;
• b. supplying said second input with a second digital signal;
• c. applying said first and second digital signals to a Boolean-logic function in response to a control signal at said control terminal switching from a first logic state indicating selection of one of said first and second inputs to a second logic state indicating selection of the other of said first and second inputs, and supplying the result of said Boolean-logic function to said output for a predetermined amount of time before continuing to steps d and e;
• d. coupling said first input to said output when said control signal indicates a selection of said first input;
• and
• e. coupling said second input to said output when said control signal indicates a selection of said second input.