Serial device compaction for improving integrated circuit layouts

A flip-flop formed on a semiconductor substrate for producing an output signal based on a plurality of input signals, the flip-flop comprising:

• a first plurality of transistors of a first channel type, each of the first plurality of transistors coupled to a first supply node and a different node of at least three switchable nodes, for selectively pulling the switchable nodes to a first logic level based on the plurality of input signals, each of the switchable nodes forming a direct connection point between a drain of a transistor of the first channel type and a drain of a transistor of a second channel type, wherein all of the first plurality of transistors are formed using a first single contiguous active area disposed within the semiconductor, wherein the first contiguous active area contains no permanently inactive transistors within the flip-flop;
• and
• a second plurality of transistors of a second channel type, each of the second plurality of transistors coupled between a second supply node and a different node of said at least three switchable nodes, for selectively pulling the switchable nodes to a second logic level based on the plurality of input signals, the second plurality of transistors including at least three transistors of the second channel type, wherein all of the second plurality of transistors are formed using a second single contiguous active area disposed within the semiconductor substrate.

A logic circuit formed on a semiconductor, the logic circuit comprising:

• a least three switchable nodes;
• a first plurality of series transistor branches coupled between a first supply node and the switchable nodes for pulling the switchable nodes to a first logic level, wherein all of the first plurality of series transistor branches are disposed adjacent to each other in a first contiguous active area of the semiconductor;
• and
• a second plurality of series transistor branches coupled between a second supply node and the switchable nodes for pulling the switchable nodes to a second logic level, wherein all of the second plurality of series transistor branches are disposed adjacent to each other on the semiconductor;
• wherein at least one of the switchable nodes is coupled to an even number of said first plurality of series transistor branches and an even number of said second plurality of series transistor branches.

A method of designing a logic circuit, the method comprising:

• generating a first logic function to represent a pull-down network of the logic circuit, the pull-down network for pulling an output node down to a first logic level in response to a first predetermined combination of inputs, wherein said generating the first logic function includes using a symbolic representation corresponding to a Karnaugh map, the symbolic representation including a plurality of values representing logic ones and logic zeros, to generate the first logic function directly from the logic zeros in the symbolic representation;
• generating a second logic function to represent a pull-up network of the logic circuit, the pull-up network for pulling the output node up to a second logic level in response to a second predetermined combination of inputs, wherein said generating the second logic function includes using the symbolic representation to generate the second logic function directly from the logic ones in the symbolic representation;
• and
• designing the logic circuit to include the pull-down network and the pull-up network in accordance with the first logic function and the second logic function, respectively.