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US 6,297,663 B1Granted
Bus system
AssigneeHitachi, Ltd.
InventorsToshinobu Matsuoka, Yukihiro Seki, Tsunehiro Tobita, Shinichi Suzuki
Life of this patent
Estimating the term…
Abstract
A bus system has a bus constructed of a plurality of signal lines for transmission of signals, first and second terminating resistors provided at both ends of the respective signal lines, first, second and third modules coupled to the bus between the first and second terminating resistors and being each operative to transmit a signal through an output circuit of open drain type, first series resistors inserted in the respective signal lines between the first and second modules, and second series resistors inserted in the respective signal lines between the second and third modules.
Claims21
A bus system comprising:
- a bus constructed of a plurality of signal lines for transmission of signals;
- first and second terminating resistors provided at both ends of the bus;
- first, second and third modules each of which is operative to transmit a signal through an output circuit of open drain type, said first module connected with said bus at first junctions of said signal lines, said second module connected with said bus at second junctions of said signal lines, and said third module connected with said bus at third junctions of said signal lines;
- first series resistors inserted in a junction of the signal lines between said first and second junctions;
- and
- second series resistors inserted in a junction of the signal lines between said second and third junctions.
3 more elements
A bus system comprising:
- a bus constructed of a plurality of signal lines for transmission of signals;
- first and second terminating resistors provided at both ends of the bus;
- a plurality of modules connected with said bus at a plurality of junctions of said signal lines and being each operative to transmit a signal through an output circuit of open drain type;
- and
- series resistors provided in junction of the signal lines between said plurality of junctions of said signal lines.
2 more elements
A memory system comprising:
- a bus constructed of a plurality of signal lines for transmission of signals;
- first and second terminating resistors provided at both ends of the bus;
- a first memory buffer, a memory controller and a second memory buffer each of which is operative to transmit a signal through an output circuit of open drain type, said first memory buffer connected with said bus at first junctions of the signal lines, said memory controller connected with said bus at second junctions of the signal lines, and said second memory buffer connected with said bus at third junctions of the signal lines;
- first series resistors inserted in the signal lines between said first and second junctions;
- and
- second series resistors inserted in the signal lines between said second and third junctions.
3 more elements
A bus system comprising:
- a bus constructed of a plurality of signal lines for transmission of signals;
- first and second terminating resistors provided at both ends of the respective signal lines;
- first, second and third modules coupled to said bus between said first and second terminating resistors and being each operative to transmit a signal through an output circuit of open drain type;
- first series resistors inserted in the respective signal lines between said first and second modules;
- and
- second series resistors inserted in the respective signal lines between said second and third modules, wherein a series resultant resistance of said first terminating resistor and said first series resistor and a series resultant resistance of said second terminating resistor and said second series resistor each have a value which is in the range of from 0.8 times to 1.2 times a characteristic impedance of said bus.
3 more elements
A memory system comprising:
- a bus constructed of a plurality of signal lines for transmission of signals;
- first and second terminating resistors provided at both ends of the respective signal lines;
- a first memory buffer, a memory controller and a second memory buffer which are coupled to said bus between said first and second terminating resistors and which are each operative to transmit a signal through an output circuit of open drain type;
- first series resistors inserted in the respective signal lines between said first memory buffer and said memory controller;
- and
- second series resistors inserted in the respective signal lines between said memory controller and said second memory buffer, wherein a series resultant resistance of said first terminating resistor and said first series resistor and a series resultant resistance of said second terminating resistor and said second series resistor respectively have a value which is in the range of from 0.8 times to 1.2 times a characteristic impedance of said bus.
3 more elements
Dependencies are inferred from the claim text.