Back to results
US 6,297,526 B1Granted
Process for producing barrier-free semiconductor memory configurations
AssigneeSiemens Aktiengesellschaft
InventorsFrank Hintermaier, Carlos Mazure-Espejo
Life of this patent
Estimating the term…
Abstract
Process for producing an integrated semiconductor memory configuration, in particular one suited to the use of ferroelectric materials as storage dielectrics, in which a conductive connection between one electrode of a storage capacitor and a selection transistor is not produced until after the storage dielectric has been deposited; and a semiconductor memory configuration produced using the production process.
Claims6
An integrated semiconductor memory configuration, comprising:
- a plurality of identical memory cells each including:
- a selection transistor having a source region;
- an insulation layer having a surface and being disposed above said selection transistor;
- said insulation layer having a contact hole formed therein above said source region of said selection transistor;
- a first contact plug disposed in said contact hole and being conductively connected to said source region;
- a first electrode disposed on said surface of said insulation layer;
- a dielectric layer disposed on said first electrode;
- a second electrode disposed on said dielectric layer and being electrically isolated from said first electrode by said dielectric layer;
- a second contact plug electrically connecting said second electrode to said first contact plug and being electrically isolated from said first electrode by a portion of said dielectric layer;
- and
- a structured auxiliary layer disposed between said surface of said insulation layer and said first electrode;
- said auxiliary layer being formed with a cutout disposed above said contact hole and above regions of said surface of said insulation layer adjacent said cutout.
9 more elements
An integrated semiconductor memory configuration comprising:
- a plurality of identical memory cells each including:
- a selection transistor having a source region;
- an insulation layer having a surface and being disposed above said selection transistor;
- said insulation layer having a contact hole formed therein above said source region of said selection transistor;
- a first contact plug disposed in said contact hole and being conductively connected to said source region;
- a structured auxiliary layer disposed on said surface of said insulation layer;
- said auxiliary layer being formed with a cutout disposed above said contact hole and above regions of said surface of said insulation layer adjacent said cutout;
- a first electrode disposed on said structured auxiliary layer;
- a dielectric layer disposed on said first electrode;
- a second electrode disposed on said dielectric layer and being electrically isolated from said first electrode by said dielectric layer;
- and
- a second contact plug electrically connecting said second electrode to said first contact plug and being electrically isolated from said first electrode by a portion of said dielectric layer.
9 more elements
Dependencies are inferred from the claim text.