Transistors with low overlap capacitance

A fabrication method for forming a deep sub-micron CMOS FET device with localized regions of low dielectric constant, K, oxide (where K=<3.5) in gate to drain and gate to source overlap regions, for the purpose of reducing overlap capacitance, comprising the steps of:

• (a) depositing a first oxide layer over a semiconductor substrate;
• (b) patterning and etching out said first oxide layer in order to define an eventual gate region;
• (c) depositing or growing a thin low dielectric constant, K, gate oxide on the silicon surface, corresponding to said eventual gate region;
• (d) depositing an overlying silicon nitride layer and subsequently anisotropically etching back said nitride layer to form nitride spacers on the side walls of said gate region within said first oxide layer;
• (e) etching out that portion of said low K gate oxide, which is not protected by said nitride spacers, thereby exposing the underlying silicon surface while still allowing localized regions of said low K gate oxide to remain under said nitride spacers;
• (f) growing a conventional thermal gate oxide on said exposed silicon surface, in order to complete the creation of a gate oxide layer with a graded dielectric constant;
• (g) depositing an overlying layer of polysilicon and then using a chemical mechanical polishing, CMP, process to polish back said polysilicon layer for the purpose of forming gate electrodes;
• (h) subsequent formation of conventional source-drain contacts, along with implanted N type LDD regions and implanted N+ source-drain regions as well as the doping and silicidation of said polysilicon gate electrodes.