Method of fabricating a MOS transistor with local channel ion implantation regions

A fabrication method for a MOS transistor, the method comprising steps of:

• providing a substrate with a shallow trench isolation (STI) formed within;
• forming a first gate oxide layer and a second gate oxide layer on the substrate, wherein the first gate oxide layer and the second gate oxide layer are both formed before a local channel ion implantation;
• forming a plurality of wells insulated by the STI;
• forming a pattern mask on the substrate, wherein the pattern mask serves as an implantation mask, while performing the local channel ion implantation where two implantation regions are formed in a local region of one of the wells;
• removing the pattern mask;
• repeating steps for forming the pattern mask, performing the local channel ion implantation, and removing the pattern mask, so that the two implantation regions continue to be formed in sequence in channels from the rest of the well regions;
• and
• forming a plurality of gates on the substrate, while forming source/drain (S/D) regions in the substrate.

A method of fabricating a MOS transistor, comprising steps of:

• providing a substrate with a shallow trench isolation (STI) formed within;
• forming a first gate oxide layer and second gate oxide layer on the substrate, wherein the first gate oxide layer and the second gate oxide layer are both formed before a local channel ion implantation;
• forming a first well and a second well in the substrate, wherein the first well and the second well correspond to the first gate oxide layer and the second gate oxide layer, respectively, while a first implantation region and a second implantation region are formed simultaneously as a whole in the first well and the second well so as to serve as threshold voltage adjustment regions and anti-punch through regions, and the first well and the second well are of the same conductive type;
• forming a third well and a fourth well in the substrate, wherein the third well and fourth well correspond to the first gate oxide layer and the second gate oxide layer, respectively, while a third implantation region and a fourth implantation region are formed simultaneously as a whole in the third well and the fourth well so as to provide a threshold voltage adjustment and an anti-punch through layer, and the third well and the fourth well are of the same conductive type but is different from that of the first well and the second well;
• performing the local channel ion implantation, so that a fifth implantation region and a sixth implantation region are formed in a channel region of the first well and the third well, respectively, to provide the threshold voltage adjustment and the anti-punch through layer;
• and
• forming a plurality of gates on the substrate, while forming source/drain (S/D) regions in the substrate.