Back to results
US 6,295,636 B1Granted
RTL analysis for improved logic synthesis
AssigneeLSI Logic Corporation
InventorGuy Dupenloup
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeLSI Logic Corporation
InventorGuy Dupenloup
Estimating the term…
A method of generating synthesis scripts to synthesize integrated circuit (IC) designs in RTL level description into gate-level description comprising the steps of identifying hardware elements in the RTL code, determining key pins for each of said identified hardware elements, extracting design structure and hierarchy from the RTL code, generating script to cause a logic synthesis tool to apply bottom-up synthesis to modules and sub-modules of the IC design, generating script to cause a logic synthesis tool to apply top-down characterization to modules and sub-modules of the IC design and generating script to cause a logic synthesis tool to repeat said bottom-up and said top-down applications until certain predetermined constraints are satisfied.
A method of generating synthesis scripts to synthesize integrated circuit (IC) designs in RTL code into a gate-level description, said method comprising the steps of:
An apparatus for facilitating synthesis of integrated circuit (IC) designs in RTL code into a gate-level description, comprising:
A computer storage medium containing instructions for facilitating synthesis of integrated circuit (IC) designs in RTL code into a gate-level description, said instructions comprising the steps of:
A process for facilitating synthesis of integrated circuit (IC) designs in RTL code into a gate-level description, said process comprising the steps of:
Dependencies are inferred from the claim text.