Logic synthesis method and device using similar circuit extraction

Abstract

A logic synthesizer includes a circuit analyzer for reading hardware function operation descriptions in hardware description language to translate the same into internal circuit expressions, a memory for storing circuits, common part information and restriction information, a hierarchically low level separator for separating hierarchically low level information that is commonly referenced, an output device for outputting a synthesis result, an optimization device for optimization processing, and a restriction condition input device for inputting restriction conditions. The circuit analyzer includes a basic analyzing device for basic analysis of the hardware descriptions, a similar description extraction element for extracting common and similar descriptions, and a hierarchically low level common device for translating the extracted common descriptions into common reference form at a hierarchically low level.

Dependencies are inferred from the claim text.