Memory test facilitation circuit using stored test data repeatedly

A method of testing a memory device having a main memory circuit and an auxiliary memory circuit, comprising the steps of:

• transferring test data from external test equipment to said auxiliary memory circuit;
• storing said test data in said auxiliary memory circuit;
• generating a status signal indicating that said test data have been stored in said auxiliary memory circuit;
• transferring said test data from said auxiliary memory circuit to one location in said main memory circuit, responsive to said status signal;
• receiving a write request signal from said external test equipment;
• and
• transferring said test data from said auxiliary memory circuit to another location in said main memory circuit, responsive to said write request signal.

A test facilitation circuit integrated into a memory device having a main memory circuit with a plurality of memory cells, to facilitate testing of said main memory circuit by external test equipment, comprising:

• a first auxiliary memory circuit storing test data;
• an internal data bus coupling said first auxiliary memory circuit to said main memory circuit;
• an interface circuit receiving address information, a read request signal, and a write request signal from said external test equipment, and transferring said test data to and from said external test equipment;
• an auxiliary memory controller coupled to said interface circuit, controlling access to said first auxiliary memory circuit;
• and
• a main memory controller coupled to said interface circuit, receiving a first test mode signal from said external test equipment, responding to said write request signal when said first test mode signal is in one state by directing said auxiliary memory controller to transfer said test data from said interface circuit to said first auxiliary memory circuit, and responding to said write request signal when said first test mode signal is another state by transferring test data immediately from said first auxiliary memory circuit to said main memory circuit;
• wherein said auxiliary memory controller sends said main memory controller a status signal, indicating storage of said test data in said auxiliary memory, upon completion of transfer of said test data from said interface circuit to said first auxiliary memory circuit, and when said first test mode signal is in said one state, said main memory controller transfers said test data from said first auxiliary memory circuit to said main memory circuit responsive to said status signal.

A method of testing a memory device having a main memory circuit, an auxiliary memory circuit, and an interface circuit, comprising the steps of:

• sending address information, a first test mode signal, a read request signal, and a write request signal from external test equipment to said interface circuit;
• when said first test mode signal is in a first state, and in response to said write request signal:
• transferring test data from said external test equipment to said interface circuit;
• storing said test data in said auxiliary memory circuit;
• and
• transferring said test data from said auxiliary memory circuit to said main memory circuit;
• and
• when said first test mode signal is in a second state, and in response to said write request signal:
• transferring test data previously stored in said auxiliary memory circuit to said main memory circuit.