Apparatus and method for improved vector processing to support extended-length integer arithmetic

A vector computer comprising:

• a memory;
• an input-output subsystem including magnetic disk drives;
• a plurality of vector element registers, each vector element register coupled to the memory and operable to be selectively loaded with data from the memory, each vector element register including a plurality of N elements, and each element having a plurality of bits;
• a vector carry register, the vector carry register including a plurality of N bits;
• and
• a vector arithmetic or logical functional unit having an input coupled to receive data operands from the respective elements of two of the plurality of vector element registers and the vector carry register, and operable to produce a result as an output, wherein each element of the result is based on an element from the first vector element register, a corresponding element from the second vector element register, and a corresponding bit from the vector carry register;
• and
• a controller associated with the vector registers and responsive to program instructions to successively transmit one or more corresponding elements from each of the two vector element registers and one or more corresponding bits from the vector carry register to the functional unit and to successively store results from the output of the functional unit as elements into one of the plurality of vector element registers, further comprising:
• means for initializing the vector carry register with a plurality of N bits which are each zero;
• means for loading low-order bits of each one of N extended-precision numbers of a first addend vector from the memory into successive elements of a first one of the plurality of vector element registers;
• means for loading low-order bits of each one of N extended-precision numbers of a second addend vector from the memory into successive elements of a second one of the plurality of vector element registers;
• means for storing low-order bits of each one of N extended-precision numbers of a resulting sum vector to the memory from successive elements of a third one of the plurality of vector element registers, wherein each one of N extended-precision numbers of the resulting sum vector is a sum of a corresponding bit of the vector carry register, a corresponding element of the first vector element register, and a corresponding element of the second vector element register;
• means for loading next-higher-order bits of each one of N extended-precision numbers of a first addend vector from the memory into successive elements of the first one of the plurality of vector element registers;
• means for loading next-higher-order bits of each one of N extended-precision numbers of a second addend vector from the memory into successive elements of the second one of the plurality of vector element registers;
• and
• means for storing next-higher-order bits of each one of N extended-precision numbers of a resulting sum vector to the memory from successive elements of the third one of the plurality of vector element registers, wherein each one of N extended-precision numbers of the resulting sum vector is a sum of a corresponding bit of the vector carry register, a corresponding element of the first vector element register, and a corresponding element of the second vector element register;
• and wherein the vector carry register is first loaded with carry-out bits of addition operations of the low-order bits, wherein said carry-out bits of the addition operations of the low-order bits are used as carry-in bits for addition operations of the next-higher-order bits, and wherein the vector carry register is next loaded with carry-out bits of addition operations of the next-higher-order bits.

A method of processing vectors in a computer having a main memory, a plurality of vector element registers, each vector element register holding a plurality of elements of an ordered set of data, a vector carry register holding a plurality of bits of an ordered set of data, and at least one pipelined arithmetic or logical functional unit for receiving successive inputs of operands while holding data for operations still being completed and for delivering successive operation results, the method comprising:

• selectively transmitting data from the main computer memory to the vector registers for storage as a plurality of elements of an ordered set of data;
• initializing the vector carry register with an ordered set of bits;
• selecting from the plurality of vector registers at least one vector register as an operand vector register to provide operands, and one vector register to receive results;
• successively inputting the elements of the ordered set of data from the selected operand vector register and bits of the vector carry register to the functional unit on successive clock periods;
• and
• successively outputting results produced by the functional unit as elements of an ordered set to the selected result vector register and as bits of an ordered set of bits to the vector carry register on successive clock periods following delivery of a first result from the functional unit.

A method of processing vectors in a computer having a main memory, a plurality of vector element registers, each vector element register holding a plurality of elements of an ordered set of data, a vector carry register holding a plurality of bits of an ordered set of data, and at least one pipelined arithmetic or logical functional unit for receiving successive inputs of operands while holding data for operations still being completed and for delivering successive operation results, the method comprising:

• selectively transmitting data from the main computer memory to the vector registers for storage as a plurality of elements of an ordered set of data;
• initializing the vector carry register with an ordered set of bits;
• selecting from the plurality of vector registers at least one vector register as an operand vector register to provide operands, and one vector register to receive results;
• successively inputting the elements of the ordered set of data from the selected operand vector register and bits of the vector carry register to the functional unit on successive clock periods;
• and
• successively outputting results produced by the functional unit as elements of an ordered set to the selected result vector register and as bits of an ordered set of bits to the vector carry register on successive clock periods following delivery of a first result from the functional unit, further comprising:
• initializing a plurality of carry-in bits in the vector carry register;
• loading elements of a first vector element register with lowest-order bits of each of a first plurality of numbers from the main memory;
• loading elements of a second vector element register with lowest-order bits of each of a second plurality of numbers from the main memory;
• successively adding a pair of elements, one each from the first and second vector element registers, with a corresponding carry-in bit from the vector carry register as operands to the functional unit, and outputting successively sum and carry-out results from the functional unit to a third vector element register and the vector carry register respectively;
• storing elements of the third vector element register to lowest-order bits of each of a third plurality of numbers in main memory;
• loading elements of the first vector element register with next-lowest-order bits of each of the first plurality of numbers from the main memory;
• loading elements of the second vector element register with next-lowest-order bits of each of the second plurality of numbers from the main memory;
• successively adding a pair of elements, one each from the first and second vector element registers, with a corresponding carry-in bit from the vector carry register as operands to the functional unit and outputting successively sum and carry-out results from the functional unit to the third vector element register and the vector carry register respectively;
• and
• storing elements of the third vector element register to next-lowest-order bits of each of the third plurality of numbers in main memory.

A method of processing vectors in a computer having a main memory, a plurality of vector element registers, each vector element register holding a plurality of elements of an ordered set of data, a vector carry register holding a plurality of bits of an ordered set of data, and at least one pipelined arithmetic or logical functional unit for receiving successive inputs of operands while holding data for operations still being completed and for delivering successive operation results, the method comprising:

• selectively transmitting data from the main computer memory to the vector registers for storage as a plurality of elements of an ordered set of data;
• initializing the vector carry register with an ordered set of bits;
• selecting from the plurality of vector registers at least one vector register as an operand vector register to provide operands, and one vector register to receive results;
• successively inputting the elements of the ordered set of data from the selected operand vector register and bits of the vector carry register to the functional unit on successive clock periods;
• and
• successively outputting results produced by the functional unit as elements of an ordered set to the selected result vector register and as bits of an ordered set of bits to the vector carry register on successive clock periods following delivery of a first result from the functional unit, further comprising:
• initializing a plurality of borrow-in bits in the vector carry register;
• loading elements of a first vector element register with lowest-order bits of each of a first plurality of numbers from the main memory;
• loading elements of a second vector element register with lowest-order bits of each of a second plurality of numbers from the main memory;
• successively subtracting a pair of elements, one each from the first and second vector element registers, with a corresponding borrow-in bit from the vector carry register as operands to the functional unit, and outputting successively difference and borrow-out results from the functional unit to a third vector element register and the vector carry register respectively;
• storing elements of the third vector element register to lowest-order bits of each of a third plurality of numbers in main memory;
• loading elements of the first vector element register with next-lowest-order bits of each of the first plurality of numbers from the main memory;
• loading elements of the second vector element register with next-lowest-order bits of each of the second plurality of numbers from the main memory;
• successively subtracting a pair of elements, one each from the first and second vector element registers, with a corresponding borrow-in bit from the vector carry register as operands to the functional unit, and outputting successively difference and borrow-out results from the functional unit to a third vector element register and the vector carry register respectively;
• and
• storing elements of the third vector element register to next-lowest-order bits of each of the third plurality of numbers in main memory.

A vector processor comprising:

• a plurality of vector element registers including a first and a second vector element register, each vector element register coupled to the memory and operable to be selectively loaded with data from a memory, each vector element register including a plurality of N elements, and each element having a plurality of bits;
• a vector carry register, the vector carry register including a plurality of N bits;
• and
• a vector arithmetic functional unit having an input coupled to receive data operands from successive elements of two of the plurality of vector element registers and the vector carry register, and operable to produce a result, the result having successive elements and carry-out bits, wherein each element and carry-out bit of the result is based on an element from the first vector element register, a corresponding element from the second vector element register, and a corresponding carry-in bit from the vector carry register;
• and
• a controller associated with the vector registers and responsive to program instructions to successively transmit a corresponding element from each one of the two vector element registers and a corresponding bit from the vector carry register to the functional unit and to successively store results from the output of the functional unit as elements into one of the plurality of vector element registers and as bits into the vector carry register.

A vector processor comprising:

• a plurality of vector element registers including a first and a second vector element register, each vector element register coupled to the memory and operable to be selectively loaded with data from a memory, each vector element register including a plurality of N elements, and each element having a plurality of bits;
• a vector carry register, the vector carry register including a plurality of N bits;
• and
• a vector arithmetic functional unit having an input coupled to receive data operands from successive elements of two of the plurality of vector element registers and the vector carry register, and operable to produce a result, the result having successive elements and carry-out bits, wherein each element and carry-out bit of the result is based on an element from the first vector element register, a corresponding element from the second vector element register, and a corresponding carry-in bit from the vector carry register;
• and
• a controller associated with the vector registers and responsive to program instructions to successively transmit a corresponding element from each one of the two vector element registers and a corresponding bit from the vector carry register to the functional unit and to successively store results from the output of the functional unit as elements into one of the plurality of vector element registers and as bits into the vector carry register, further comprising:
• means for initializing the vector carry register with a plurality of N bits which are each zero;
• means for loading low-order bits of each one of N extended-precision numbers of a first addend vector from the memory into successive elements of a first one of the plurality of vector element registers;
• means for loading low-order bits of each one of N extended-precision numbers of a second addend vector from the memory into successive elements of a second one of the plurality of vector element registers;
• means for storing low-order bits of each one of N extended-precision numbers of a resulting sum vector to the memory from successive elements of a third one of the plurality of vector element registers, wherein each one of N extended-precision numbers of the resulting sum vector is a sum of a corresponding bit of the vector carry register, a corresponding element of the first vector element register, and a corresponding element of the second vector element register;
• means for loading next-higher-order bits of each one of N extended-precision numbers of a first addend vector from the memory into successive elements of the first one of the plurality of vector element registers;
• means for loading next-higher-order bits of each one of N extended-precision numbers of a second addend vector from the memory into successive elements of the second one of the plurality of vector element registers;
• and
• means for storing next-higher-order bits of each one of N extended-precision numbers of a resulting sum vector to the memory from successive elements of the third one of the plurality of vector element registers, wherein each one of N extended-precision numbers of the resulting sum vector is a sum of a corresponding bit of the vector carry register, a corresponding element of the first vector element register, and a corresponding element of the second vector element register;
• and wherein the vector carry register is first loaded with carry-out bits of addition operations of the low-order bits, wherein said carry-out bits of the addition operations of the low-order bits are used as carry-in bits for addition operations of the next-higher-order bits, and wherein the vector carry register is next loaded with carry-out bits of addition operations of the next-higher-order bits.

A vector processor comprising:

• a plurality of vector element registers including a first and a second vector element register, each vector element register coupled to the memory and operable to be selectively loaded with data from a memory, each vector element register including a plurality of N elements, and each element having a plurality of M bits;
• and
• a vector carry register, the vector carry register including a plurality of N elements, each of which has a single bit;
• wherein the vector processor is operable to obtain an M-bit element from one of the plurality of vector element registers and a one-bit operand from the vector carry register as operands for an operation.