Method and structure for accessing a reduced address space of a defective memory
AssigneeTower Semiconductor Ltd.
InventorsEli Wildenberg, Gennady Goltman
Life of this patent
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AssigneeTower Semiconductor Ltd.
InventorsEli Wildenberg, Gennady Goltman
Estimating the term…
A circuit and method for producing defect tolerant high density memory cells at a low cost is disclosed. Rather than using redundant memory cells to salvage a memory circuit having non-functional memory cells, an address mapping circuit is used to remap addresses for non-functional memory cells into addresses for functional memory cells. Specifically, if the memory array of a memory circuit includes non-functional memory cells, an address mapping scheme is selected to reduce the effective size of the memory circuit so only functional memory cells are addressed. Because redundant memory cells are not included in the memory circuit, the semiconductor area and the cost of the memory circuit is reduced.
A memory circuit having an address bus and a data bus, the memory circuit comprising:
Dependencies are inferred from the claim text.