Method and apparatus for assuring cache coherency

A processing system comprising:

• a client process;
• a memory that includes a plurality of blocks,
• a cache memory operably coupled to temporarily store at least some of the plurality of blocks at a plurality of cache locations in the cache memory;
• an operation generator operably coupled to receive client commands from the client process, wherein each of the client commands includes a memory address associated with one of the plurality of blocks having a block address, and wherein the operation generator generates fill commands, flush commands, and memory commands based on the client commands, such that:
• each of the fill commands includes the block address and the cache location to which the block of memory is to be stored,
• each of thee flush commands includes the block address and the cache location from which the block of memory is to be stored, and
• each of the memory commands includes a cache address relative to the cache location, corresponding to the memory address relative to the block address;
• a fill buffer operably coupled to temporarily store the fill commands;
• a memory command buffer operably coupled to temporarily store the memory commands;
• a flush buffer operably coupled to temporarily store the flush commands;
• a memory control operably coupled to the fill buffer, the flush buffer, and the memory command buffer to process the fill commands, the flush commands, and the memory commands, and, therefrom, effect a transfer of data to perform the data commands;
• and
• wherein the operation generator generates the fill commands, the flush commands, and the memory control commands in a first sequential order, and the memory control processes the fill commands, the flush commands, and the memory commands in a second sequential order.

A method of memory access comprising the steps of:

• receiving client commands from a client process;
• generating fill commands, flush commands, and memory commands, based on the client commands;
• storing the fill commands in a fill buffer;
• storing the flush commands in a flush buffer;
• storing the memory commands in a memory command buffer;
• processing the fill commands to store a source memory block of a plurality of memory blocks into a destination cache location of a plurality of cache locations;
• processing the flush commands to store a source cache location of the plurality of cache locations into a destination memory block of the plurality of memory blocks;
• processing the memory commands to transfer a data item to and from a cache location of the plurality of cache locations from and to the client process;
• wherein processing of the fill commands is independent of the processing of the flush commands and independent of the processing of the memory commands;
• and
• the processing of the memory commands is dependent upon the processing of the fill commands.

A memory access system comprising:

• a memory that includes a plurality of memory blocks,
• a cache memory that includes a plurality of cache locations,
• a cache controller operably coupled to receive client commands from a client process, wherein the cache controller generates fill commands, flush commands, and memory commands, based on the client commands;
• a fill processor operably coupled to process the fill commands and store a source memory block of the plurality of memory blocks into a destination cache location of the plurality of cache locations;
• a flush processor operably coupled to process the flush commands and store a source cache location of the plurality of cache locations into a destination memory block of the plurality of memory blocks;
• and
• a memory command processor operably coupled to process the memory commands and transfer a data item to and from a cache location of the plurality of cache locations from and to the client process;
• and wherein
• the cache controller generates the fill commands and the flush commands in a sequential order, and
• the processing of the fill commands and the flush commands are independent of the sequential order generated by the cache controller.

A processing system comprising:

• a client process;
• a memory that includes a plurality of blocks,
• a cache memory operably coupled to temporarily store at least some of the plurality of blocks at a plurality of cache locations in the cache memory;
• an operation generator operably coupled to receive client commands from the client process, wherein each of the client commands includes a memory address associated with one of the plurality of blocks having a block address, and wherein the operation generator generates fill commands, flush commands, and memory commands based on the client commands, such that:
• each of the fill commands includes the block address and the cache location to which the block of memory is to be stored,
• each of thee flush commands includes the block address and the cache location from which the block of memory is to be stored, and
• each of the memory commands includes a cache address relative to the cache location, corresponding to the memory address relative to the block address;
• a fill buffer operably coupled to temporarily store the fill commands;
• a memory command buffer operably coupled to temporarily store the memory commands;
• a flush buffer operably coupled to temporarily store the flush commands;
• a memory control operably coupled to the fill buffer, the flush buffer, and the memory command buffer to process the fill commands, the flush commands, and the memory commands, and, therefrom, effect a transfer of data to perform the data commands;
• and
• wherein the client process includes a transmit buffer and a receive buffer for communicating data to and from the cache memory, and
• the memory commands include read commands and write commands, and wherein the memory control:
• processes the read commands so as to effect the transfer of data from the cache memory to the receive buffer, and
• processes the write commands so as to effect the transfer of data from the transmit buffer to the cache memory.

A method of memory access comprising the steps of:

• receiving client commands from a client process;
• generating fill commands, flush commands, and memory commands, based on the client commands;
• storing the fill commands in a fill buffer;
• storing the flush commands in a flush buffer;
• storing the memory commands in a memory command buffer;
• processing the fill commands to store a source memory block of a plurality of memory blocks into a destination cache location of a plurality of cache locations;
• processing the flush commands to store a source cache location of the plurality of cache locations into a destination memory block of the plurality of memory blocks;
• processing the memory commands to transfer a data item to and from a cache location of the plurality of cache locations from and to the client process;
• wherein the client commands are received from the client process in a first sequential order;
• and
• the processing of the fill commands, the flush commands, and the memory commands is in a second sequential order.