US 6,295,579 B1 · Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas

Abstract

A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.

Claims4

Dependent claims

A processor system comprising:

a processor;
a memory storing local data accessible by said processor;
a first cache holding a copy of remote data to be accessed by said processor when an access request by said processor is requesting an access of remote data located in another processor system connected to said processor system,
a remote access circuit connected to said first cache for sending and receiving data to and from said another processor system;
and
a second cache for holding a copy of said local data to be accessed by said processor when the access request by said processor is requesting an access of said local data;
wherein the access request requesting an access of remote data only affects said copy of remote data in said first cache without affecting the copy of said local data in said second cache.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

09/070,851Filed 1 May 1998 · continuation

Priority

JP 6-1747684 Jul 1994

Granted

25 Sep 2001

Term ends

Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 12/0813
Multiuser, multiprocessor or multiprocessing cache systems: with a network or matrix configuration
G06F 12/0848
Cache with multiple tag or data arrays being simultaneously accessible: partitioned cache, e.g. separate instruction and operand caches
G06F 2212/272
Using a specific cache architecture: cache only memory architecture [COMA]
G06F
Computing and data processing

Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas

Life of this patent

Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas

Life of this patent

Abstract

Claims4