Control system for recreating of data output clock frequency which matches data input clock frequency during data transferring

In an input digital data receiving and transport system, a method for controlling a voltage controlled oscillator to re-create an output frequency Fr to regulate the output data rate of a FIFO data register which receives bursts of incoming data at an incoming frequency rate of If, said method comprising the steps of:

• (a) loading said FIFO register with incoming serial digital data at a frequency rate If;
• (b) loading a difference generator (G,4) with said incoming serial data at the frequency rate If and decrementing this frequency rate, If, by a first feedback signal Fri from a voltage controlled oscillator and a second feedback digital signal which represents the FIFO loading status, in order to develop a difference signal Y;
• (c) feeding said difference signal Y to a driver module to develop a control signal Yo;
• (d) using said control signal Yo to regulate a voltage controlled oscillator 10;
• (e) utilizing the output frequency Fr of said voltage controlled oscillator to control the output clocking frequency data rate of said FIFO.

A data transport system for regulating the transfer rate of incoming serial digital data and headers received from a remote transmitter at an original clock rate, F0, to a FIFO register after removal of headers comprising:

• (a) means to load said incoming serial digital data without headers into a FIFO register at an incoming frequency rate of If which was set to clock said incoming digital data and clock said incoming digital data and headers and wherein the frequency rate If is the expanded rate of F0 plus headers;
• (b) means to generate an output frequency data rate Fr for said FIFO register which will continuously match the remotely transmitted original digital data clocking frequency rate F0, so that said FIFO will maintain itself at a HALF-FULL status condition during normal operation, wherein said means to generate an output frequency data rate includes:
• (b1) means to generate a difference signal Y which utilizes the input rate If and is regulated by a first feedback signal Fr and a second feedback signal indicating the loading status of said FIFO register;
• (b2) means to feed said difference signal Y to a driver module to develop a control voltage Yo for a voltage controlled oscillator;
• (b3) said voltage controlled oscillator generating an output frequency clock data rate Fr which closely matches the average incoming serial data rate frequency If.

A data transport system for regulating the transfer rate of incoming serial digital data and headers, received from a remote transmitter at an original clock rate, Fo, to a FIFO register after removal of headers comprising:

• (a) means to load said incoming serial digital data without headers into an FIFO register at an incoming frequency rate of If which was set to clock said incoming digital data and headers and wherein the frequency rate If is the expanded rate of F0 plus headers;
• (b) means to generate an output frequency data rate FR for said FIFO register which will continuously match the remotely transmitted original digital data clocking frequency rate F0 so that said FIFO will maintain itself at a HALF-FULL status condition during normal operation, wherein said means to generate an output frequency digital data rate FR includes:
• (b1) difference generator means for receiving said incoming serial data at the If frequency rate and including:
• (b1a) clock arbitration logic means for receiving said incoming serial data at the If clock rate and for developing an incrementation/decrementation signal according to the feedback frequency signal rate Fr, said incrementation/decrementation signal being transmitted to a FIFO image logic unit;
• (b1b) said FIFO image logic unit operating at said If clock rate and indicating the difference between the average If clock and the output clock frequency Fr, and includes:
• (b1b1) an image counter which develops an 8-bit digital signal indicating the loading status of said FIFO register;
• (b1c) a pulse logic unit for receiving said 8-bit FIFO loading status signal from said image counter and including:
• (b1c1) means to utilize the 3 most significant bits of said 8-bit FIFO loading status signal as an exponential power of “2” in order to control a pulse period counter to said driver;
• (b1c2) means to regulate a pulse width counter signal to said driver module according to the FIFO loading status signal developed by said image logic;
• (b1d) said driver module for receiving the output signal Y from said pulse logic unit and including:
• (b1d1) an R-C voltage stabilizing circuit to provide an output voltage Yo;
• (b1e) a voltage-controlled oscillator for receiving said voltage signal Yo and generating the output frequency data clock rate Fr for said FIFO register.