Frequency multiplier using delayed lock loop (DLL)

An output circuit for a frequency multiplier, comprising:

• a voltage-controlled delay unit that varies a delay ratio of an input signal and outputs a divided signal based on a difference between the input signal and a feed-back signal;
• a first output circuit receives a first pair of signals from the voltage-controlled delay unit and outputs a first duty cycle signal;
• a second output circuit that receives a second pair of signals from the voltage-controlled delay line and outputs a second duty cycle signal;
• and
• a logic circuit that logically processes the first and second duty cycle signals from the first and second output circuits to output a signal with a predetermined duty cycle.

A frequency multiplier, comprising:

• a detector that detects a difference between an input signal and a feed-back signal and outputs a control signal based on the detected difference;
• a voltage-controlled delay line that varies a delay of the input signal and outputs the feed-back signal based on the control signal, wherein the voltage-controlled delay includes a plurality of delay elements;
• a first output circuit that receives a first input/output pair of delay element signals from the voltage-controlled delay line and outputs a first duty cycle signal;
• a second output circuit that receives a second input/output pair of delay element signals from the of the voltage-controlled delay line and outputs a second duty cycle signal;
• and
• a circuit that logically processes the first and second duty cycle signals from the first and second output circuits to output a signal with a prescribed duty cycle.