US 6,295,300 B1 · Circuit and method for symmetric asynchronous interface

Abstract

A symmetric asynchronous interface circuit for interfacing between two asynchronously operating devices has a first and third synchronization circuits for synchronizing a READY signal outputted by a transmitting device to a clock signal on the side of a receiving device and outputting the synchronized READY signal to the receiving device, first and second delay circuits for delaying a signal corresponding to the synchronized READY signal outputted by the first/third synchronization circuit and outputting the delayed signal as an ACKNOWLEDGE signal, second and fourth synchronization circuits for synchronizing the ACKNOWLEDGE signal outputted by the first/second delay circuit to a clock signal on the side of the transmitting device, and first and second pulse generation circuits for generating a pulse signal when the synchronized ACKNOWLEDGE signal is supplied from the second/fourth synchronization circuit and outputting the pulse signal to the transmitting device as an ACKNOWLEDGE signal.

Claims42

Dependent claims

A symmetric asynchronous interface circuit which is utilized for interfacing between a first device and a second device which operate asynchronously, comprising:

a first synchronization circuit which receives a READY signal outputted by a control section of the first device, synchronizes the READY signal to a clock signal on the side of the second device, and outputs the synchronized READY signal to a control section of the second device;
a first delay circuit for delaying a signal corresponding to the synchronized READY signal outputted by the first synchronization circuit and outputting the delayed signal as an ACKNOWLEDGE signal;
a second synchronization circuit which synchronizes the ACKNOWLEDGE signal outputted by the first delay circuit to a clock signal on the side of the first device;
a first pulse generation circuit which generates a pulse signal when the synchronized ACKNOWLEDGE signal is supplied from the second synchronization circuit and outputs the pulse signal to the control section of the first device as an ACKNOWLEDGE signal;
a third synchronization circuit which receives a READY signal outputted by the control section of the second device, synchronizes the READY signal to the clock signal on the side of the first device, and outputs the synchronized READY signal to the control section of the first device;
a second delay circuit for delaying a signal corresponding to the synchronized READY signal outputted by the third synchronization circuit and outputting the delayed signal as an ACKNOWLEDGE signal;
a fourth synchronization circuit which synchronizes the ACKNOWLEDGE signal outputted by the second delay circuit to the clock signal on the side of the second device;
and
a second pulse generation circuit which generates a pulse signal when the synchronized ACKNOWLEDGE signal is supplied from the fourth synchronization circuit and outputs the pulse signal to the control section of the second device as an ACKNOWLEDGE signal.

6 more elements

A symmetric asynchronous interface circuit which is utilized for interfacing between a first device and a second device which operate asynchronously, comprising:

a first synchronization circuit which receives a READY signal outputted by a control section of the first device, synchronizes the READY signal to a clock signal on the side of the second device, and outputs the synchronized READY signal to a control section of the second device;
a first delay circuit for delaying a signal corresponding to the synchronized READY signal outputted by the first synchronization circuit and outputting the delayed signal as an ACKNOWLEDGE signal;
a second synchronization circuit which synchronizes the ACKNOWLEDGE signal outputted by the first delay circuit to a clock signal on the side of the first device and outputs the synchronized ACKNOWLEDGE signal to the control section of the first device;
a third synchronization circuit which receives a READY signal outputted by the control section of the second device, synchronizes the READY signal to the clock signal on the side of the first device, and outputs the synchronized READY signal to the control section of the first device;
a second delay circuit for delaying a signal corresponding to the synchronized READY signal outputted by the third synchronization circuit and outputting the delayed signal as an ACKNOWLEDGE signal;
and
a fourth synchronization circuit which synchronizes the ACKNOWLEDGE signal outputted by the second delay circuit to the clock signal on the side of the second device and outputs the synchronized ACKNOWLEDGE signal to the control section of the second device.

4 more elements

A symmetric asynchronous interface circuit which is utilized for interfacing between a first device and a second device which operate asynchronously, comprising:

a first synchronization circuit which receives a READY signal outputted by a control section of the first device, synchronizes the READY signal to a clock signal on the side of the second device, and outputs the synchronized READY signal to a control section of the second device;
a second synchronization circuit which receives an ACKNOWLEDGE signal which corresponds to the output of the first synchronization circuit and synchronizes the ACKNOWLEDGE signal to a clock signal on the side of the first device;
a first pulse generation circuit which generates a pulse signal when the synchronized ACKNOWLEDGE signal is supplied from the second synchronization circuit and outputs the pulse signal to the control section of the first device as an ACKNOWLEDGE signal;
a third synchronization circuit which receives a READY signal outputted by the control section of the second device, synchronizes the READY signal to the clock signal on the side of the first device, and outputs the synchronized READY signal to the control section of the first device;
a fourth synchronization circuit which receives an ACKNOWLEDGE signal which corresponds to the output of the third synchronization circuit and synchronizes the ACKNOWLEDGE signal to the clock signal on the side of the second device;
and
a second pulse generation circuit which generates a pulse signal when the synchronized ACKNOWLEDGE signal is supplied from the fourth synchronization circuit and outputs the pulse signal to the control section of the second device as an ACKNOWLEDGE signal.

4 more elements

A symmetric asynchronous interface method for interfacing between a first device and a second device which operate asynchronously, comprising the steps of:

a first synchronization step in which a READY signal outputted by a control section of the first device is synchronized to a clock signal on the side of the second device and the synchronized READY signal is supplied to a control section of the second device;
a first delay step in which an ACKNOWLEDGE signal is generated by delaying a signal corresponding to the synchronized READY signal of the first synchronization step;
a second synchronization step in which the ACKNOWLEDGE signal generated in the first delay step is synchronized to a clock signal on the side of the first device and thereby a synchronized ACKNOWLEDGE signal is generated;
a first pulse generation step in which a pulse signal corresponding to the synchronized ACKNOWLEDGE signal of the second synchronization step is generated and the pulse signal is supplied to the control section of the first device as an ACKNOWLEDGE signal;
a third synchronization step in which a READY signal outputted by the control section of the second device is synchronized to the clock signal on the side of the first device and the synchronized READY signal is supplied to the control section of the first device;
a second delay step in which an ACKNOWLEDGE signal is generated by delaying a signal corresponding to the synchronized READY signal of the third synchronization step;
a fourth synchronization step in which the ACKNOWLEDGE signal generated in the second delay step is synchronized to the clock signal on the side of the second device and thereby a synchronized ACKNOWLEDGE signal is generated;
and
a second pulse generation step in which a pulse signal corresponding to the synchronized ACKNOWLEDGE signal of the fourth synchronization step is generated and the pulse signal is supplied to the control section of the second device as an ACKNOWLEDGE signal.

6 more elements

A symmetric asynchronous interface method for interfacing between a first device and a second device which operate asynchronously, comprising the steps of:

a first synchronization step in which a READY signal outputted by a control section of the first device is synchronized to a clock signal on the side of the second device and the synchronized READY signal is supplied to a control section of the second device;
a first delay step in which an ACKNOWLEDGE signal is generated by delaying a signal corresponding to the synchronized READY signal of the first synchronization step;
a second synchronization step in which the ACKNOWLEDGE signal generated in the first delay step is synchronized to a clock signal on the side of the first device and the synchronized ACKNOWLEDGE signal is supplied to the control section of the first device;
a third synchronization step in which a READY signal outputted by the control section of the second device is synchronized to the clock signal on the side of the first device and the synchronized READY signal is supplied to the control section of the first device;
a second delay step in which an ACKNOWLEDGE signal is generated by delaying a signal corresponding to the synchronized READY signal of the third synchronization step;
and
a fourth synchronization step in which the ACKNOWLEDGE signal generated in the second delay step is synchronized to the clock signal on the side of the second device and the synchronized ACKNOWLEDGE signal is supplied to the control section of the second device.

4 more elements

A symmetric asynchronous interface method for interfacing between a first device and a second device which operate asynchronously, comprising the steps of:

a first synchronization step in which a READY signal outputted by a control section of the :first device is synchronized to a clock signal on the side of the second device and the synchronized READY signal is supplied to a control section of the second device;
a second synchronization step in which an ACKNOWLEDGE signal which corresponds to the synchronized READY signal of the first synchronization step is synchronized to a clock signal on the side of the first device and thereby a synchronized ACKNOWLEDGE signal is generated;
a first pulse generation step in which a pulse signal corresponding to the synchronized ACKNOWLEDGE signal of the second synchronization step is generated and the pulse signal is supplied to the control section of the first device as an ACKNOWLEDGE signal;
a third synchronization step in which a READY signal outputted by the control section of the second device is synchronized to the clock signal on the side of the first device and the synchronized READY signal is supplied to the control section of the first device;
a fourth synchronization step in which an ACKNOWLEDGE signal which corresponds to the synchronized READY signal of the third synchronization step is synchronized to the clock signal on the side of the second device and thereby a synchronized ACKNOWLEDGE signal is generated;
and
a second pulse generation step in which a pulse signal corresponding to the synchronized ACKNOWLEDGE signal of the fourth synchronization step is generated and the pulse signal is supplied to the control section of the second device as an ACKNOWLEDGE signal.

4 more elements

Dependencies are inferred from the claim text.

Circuit and method for symmetric asynchronous interface

Life of this patent

Circuit and method for symmetric asynchronous interface

Life of this patent

Abstract

Claims42