Write data input circuit

A semiconductor memory device comprising:

• a command input buffer that receives an external control signal to output an internal control signal;
• an external command latch circuit connected to the command input buffer, which latches the internal control signal synchronous with a clock signal to output a control latch signal;
• a decoder connected to the external command latch circuit, which decodes the control latch signal to generate a command;
• an internal command latch circuit connected to the decoder, which latches the command;
• a write command determination circuit that receives one of the internal control signal and the control latch signal and generates a first enable signal when the external control signal indicates a write operation;
• a data strobe input buffer that is activated in response to the first enable signal and receives data strobe signal;
• and
• a data input buffer that is activated in response to the first enable signal and receives a data signal.

A semiconductor memory device having an input pad comprising:

• a command decoder that receives and decodes a control signal to output a command;
• a transmission path from the input pad to the command decoder, for transmitting the control signal;
• a write command determination circuit coupled to the transmission path to output an enable signal when the control signal indicates a write operation;
• a data input buffer that receives data and is activated in response to the enable signal.