Dynamic random access memory device

A dynamic random access memory device, comprising:

• a plurality of word lines formed on a substrate;
• a plurality of bit-line pairs formed on said substrate;
• memory cells connected to said word lines and said bit lines, each of said memory cells comprising a transistor and a capacitor;
• a plurality of MOS differential amplifiers respectively having a pair of input nodes and including a pair of driver MOS transistors having outputs, the gates of said driver MOS transistors constituting said input nodes and being connected to said bit-line pairs;
• a BIMOS amplifier having a pair of input nodes and a pair of output nodes and including a pair of driver bipolar transistors, the bases of said bipolar transistors constituting said pair of input nodes;
• and
• a plurality of switching means for selectively connecting the output of said driver transistors to said input nodes of said BIMOS amplifier.

A dynamic random access memory device, comprising:

• a plurality of word lines formed on a substrate;
• a plurality of bit-line pairs formed on said substrate, crossing said plurality of word lines;
• memory cells connected to the crossing section of said word lines and said bit lines, each of said memory cells comprises a MOS transistors and a capacitor;
• a plurality of MOS differential amplifiers respectively having a pair of input nodes and including a pair of driver MOS transistors having output, the gates of said driver MOS transistors constituting said input nodes and connected respectively to said bit-lines pairs,
• said MOS differential amplifiers respectively having a current supply MOS transistor, the gates of said current supply MOS transistors in each MOS differential amplifier are commonly connected and supplied a fixed potential;
• a BIMOS amplifier having a pair of input nodes and a pair of output nodes and including a pair of driver bipolar transistors, the bases of said bipolar transistors constituting said input nodes;
• a plurality of switching means, each said switching means being connected in a current path between one of said driver MOS transistor outputs and one of said BIMOS amplifiers input nodes, said switching means being controlled by column select signals;
• a plurality of MOS flip-flops respectively connected between said bit-line pairs, to simultaneously amplify data read out on said bit-line pairs for restoring said read out data into said memory cells;
• and
• a pair of output lines connected to said pair of output nodes of said BIMOS amplifier.

In a dynamic random access memory device,

• a first pair of precharged bit lines;
• a first buffer differential amplifier having inputs connected to said first pair of bit lines and having first and second outputs;
• a second pair of precharged bit lines;
• a second buffer differential amplifier having inputs connected to said second pair of bit lines and having third and fourth outputs, said third output being connected in common with said first output to a first output line, said fourth outputs being connected in common with said second output to a second output line;
• means for selectively preventing communication between said first and second output lines through said buffer differential amplifiers.