Semiconductor memory device having a circuit for fast operation
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTetsushi Tanizaki, Katsumi Dosaka, Mikio Asakura
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Abstract
A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.
Claims8
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells arranged in rows and columns, and a plurality of word lines arranged corresponding to the plurality of rows of said memory cells;
- a test mode detecting circuit detecting in accordance with an external signal the fact that a test mode is set;
- and
- a control circuit being responsive to the output of said test mode detecting circuit and triggered by an external clock to perform control for conducting a disturb test on said memory cell array, said external clock including a first external signal and a second external signal having the substantially same period as the first external signal.
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells arranged in rows and columns, and a plurality of word lines arranged corresponding to the plurality of rows of said memory cells;
- a test mode detecting circuit detecting in accordance with an external signal the fact that a test mode is set;
- a control circuit being responsive to the output of said test mode detecting circuit and triggered by an external clock to perform control for conducting a disturb test on said memory cell array;
- a clock buffer for receiving said external clock;
- and
- a row select control circuit for controlling selection of the row in said memory cell array, wherein
- said control circuit is responsive to the output of said test mode detecting circuit to issue a signal determining operation timing of said row select control circuit based on the output of said clock buffer.
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells arranged in rows and columns, and a plurality of word lines arranged corresponding to the plurality of rows of said memory cells;
- a test mode detecting circuit detecting in accordance with an external signal the fact that a test mode is set;
- a control circuit being responsive to the output of said test mode detecting circuit and triggered by an external clock to perform control for conducting a disturb test on said memory cell array;
- a first buffer taking in said external clock, a second buffer taking in said external clock, and an internal clock generator generating an internal clock having double the frequency of said external clock in accordance with the outputs of said first and second buffers, wherein
- said control circuit performs the control for conducting said disturb test triggered by the internal clock.
Dependencies are inferred from the claim text.