Redundancy circuit of semiconductor memory
AssigneeKabushiki Kaisha Toshiba
InventorTakeshi Nagai
Life of this patent
Estimating the term…
Abstract
A semiconductor has eight banks that can be accessed simultaneously. Within each bank, there are disposed two fixed spare row decoders and two mapping spare row decoders. Within each bank, two fixed fuse sets are provided corresponding to the fixed spare row decoders. Eight mapping fuse sets are provided at the outside of each bank, for example, with no association with the mapping spare row decoders. Each mapping fuse set stores mapping data for determining a correspondence of the mapping fuse set to a specific mapping spare row decoder within a specific bank.
Claims38
A semiconductor memory comprising:
- a normal decoder;
- a fixed spare decoder for relieving the normal decoder;
- a fixed memory disposed in association with the fixed spare decoder;
- a mapping spare decoder for relieving the normal decoder;
- and
- a mapping memory disposed independent of the mapping spare decoder, and for being recorded with mapping data, wherein
- the normal decoder is replaced with the fixed spare decoder when a fail address for selecting the normal decoder is registered in the fixed memory, and the normal decoder is replaced with the mapping spare decoder when the fail address is registered in the mapping memory and also when the mapping data selects the mapping spare decoder.
A semiconductor memory comprising:
- a plurality of banks, each bank having a normal decoder, a fixed spare decoder for relieving the normal decoder, a fixed memory disposed in association with the fixed spare decoder, and a mapping spare decoder for relieving the normal decoder;
- and
- a mapping memory disposed at the outside of the plurality of banks, and for being registered with mapping data, wherein
- the mapping data has a function of associating the mapping memory with the mapping spare decoder within one of the plurality of banks, and
- when a fail address for selecting the normal decoder within one of the plurality of banks is registered in the mapping memory, the normal decoder is replaced with the mapping spare decoder within one of the banks associated with the mapping memory.
A semiconductor memory comprising:
- a plurality of banks, each bank having a normal decoder, a fixed spare decoder for relieving the normal decoder, a fixed memory disposed in association with the fixed spare decoder, and at least one mapping spare decoder for relieving the normal decoder;
- and
- at least one mapping memory disposed at the outside of the plurality of banks, with no association with a mapping spare decoder, and for being registered with mapping data, wherein
- the at least one mapping memory is associated with the at least one mapping spare decoder based on the mapping data registered in the at least one mapping memory, and
- when the number of the plurality of banks is expressed as 2M (M is a natural number), when the number of the at least one mapping spare decoder is expressed as S1 (S1 is a natural number), and also when the number of the at least one mapping memory is expressed as L, the following relationship of
- 1≦L≦2M×S1
- is satisfied.
Dependencies are inferred from the claim text.