US 6,295,229 B1Granted

Semiconductor device and method of operating it

AssigneeMotorola, Inc.

InventorsKuo-Tung Chang, Erwin J. Prinz, Craig T. Swift

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Abstract

A semiconductor device (70) includes a memory cell having a select transistor (67) and a storage transistor (65) having a relatively uniform tunnel dielectric thickness under both the floating gate (651) of the storage transistor and the select gate (671) of the select transistor (67). The select transistor (67) is adjacent to the drain region (68) for the memory cell to nearly eliminate a drain disturb problem. During programming, the control gate (652) is at a negative potential, and the drain region (68) is at a positive potential. The drain potential is sufficiently low to not degrade the tunnel dielectric layer (42) of the select transistor (67). During erase, a positive potential is applied to the control gate (652). The relatively uniform tunnel dielectric layer (42) thickness of the select transistor (67) allows for a faster operating device by increasing the read current of the memory device.

Claims12

Dependent claims

A method of operating a memory array, wherein the method includes selectively programming the memory array that includes a first memory cell to be programmed and a second memory cell that is not to be programmed, the selectively programming comprising:

providing a memory array including the first and second memory cells, wherein:
each of the first and second memory cells includes:
a source region, a drain/source region, and a drain region;
a floating gate overlying portions of the source region and the drain/source region;
a control gate overlying the floating gate and portions of the source region and the drain/source region;
and
a select gate overlying portions of the drain/source region and the drain region;
and
the drain regions of the first and second memory cells are electrically connected to each other;
placing the drain regions of the first and second memory cells at a first potential having a first polarity;
placing the source regions of the first and second memory cells at a second potential of approximately zero volts;
placing the control gate of the first memory cell at a third potential having a second polarity that is opposite the first polarity;
placing the select gate of the first memory cell at a fourth potential having the first polarity, wherein the fourth potential is no higher than approximately eight volts;
placing the control gate of the second memory cell at a fifth potential having an absolute value less than the first potential;
and
placing the select gate of the second memory cell at a sixth potential having an absolute value less than the first potential.

13 more elements

Dependencies are inferred from the claim text.