Phase lock loop circuit using signal estimator

A phase lock loop circuit using a signal estimator, for detecting and correcting a phase shift contained in a received signal and, in addition, removing transmission path distortion, said phase lock loop comprising:

• a signal estimator for estimating a transmission signal series using a Viterbi algorithm from the received signal and outputting the transmission signal series as an estimated signal and, in addition, outputting a minimum path metric history signal obtained as a result of temporary estimation of the signal from the current path status without traceback in the Viterbi algorithm;
• switching means which, when a control signal is active, selectively outputs the estimated signal, and, when the control signal is inactive, selectively outputs the minimum path metric history signal;
• replica generating means for generating a replica signal using a signal selected by the switching means;
• feedback loop means for detecting a phase difference contained in the received signal from the replica signal and the received signal to correct the phase difference;
• and
• control signal generating means which renders the control signal inactive when the feedback loop means is in a predetermined certain period from the start of the operation of the feedback loop means or when the phase difference detected in the feedback loop means is not less than a predetermined certain value.